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MC2 Chip
3
3-14
The encoding for the interrupt sources is shown in the next table, where
IV3-IV0 refer to bits 3-0 of the vector passed during the IACK cycle:
The priority referenced in the following table is established in the MC2
chip logic by implementing a daisy chain request/grant network. There is
a similar request/grant daisy chain at the board level.At the board level, the
MC2 chip is wired to have the highest priority followed by the
IndustryPack interface ASIC (IP2 chip) and then the VMEchip2 ASIC.
Table 3-3. Interrupt Vector Base Register Encoding and
Interrupt Source 0
unused
Timer 4
Timer 3
SCSI IRQ
LANC ERR
LANC IRQ
Timer 2
Timer 1
unused
Parity Error
unused
Serial I/O (Z85230s)
ABORT Switch
unused
Note
The Z85230 controllers have an integrated interrupt vector
register which is separate from the vector generation found
on the MC2 chip. The Z85230 also supports a scheme where
the base register value is changed based upon the interrupt
requested. During the interrupt acknowledge cycle,
interrupts from the first Z85230 have priority over those from
the second Z85230.
Priority
IV3-IV0
Daisy Chain Priority
$0 & $1 & $2
..
$3
Lowest
$4
¦
$5
|
$6
|
$7
|
$8
|
$9
|
$A
|
$B
|
$C & $D
Ø
Note 1
Next Highest
$E
Highest
$F
..
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