Vmebus Interrupter Vector Register; Mpu Status And Dma Interrupt Count Register - Motorola MVME172 Programmer's Reference Manual

VMEbus Interrupter Vector Register

ADR/SIZ
BIT
23
NAME
OPER
RESET
This register controls the VMEbus interrupter vector.

MPU Status and DMA Interrupt Count Register

ADR/SIZ
BIT 15
NAME
OPER
RESET
This is the MPU status register and DMAC interrupt counter.
MLOB
MLPE
MLBE
MCLR
http://www.mcg.mot.com/literature
$FFF40048 (8 bits of 32)
Interrupter Vector
$0F PS
$FFF40048 (8 bits of 32)
14 13 12
DMAIC
R
0 PS
When this bit is set, the MPU received a TEA and the
status indicated off-board. This bit is cleared by writing a
one to the MCLR bit in this register.
When this bit is set, the MPU received a TEA and the
status indicated a parity error during a DRAM data
transfer. This bit is cleared by writing a one to the MCLR
bit in this register. This bit is not defined for MVME172
implementation.
When this bit is set, the MPU received a TEA and
additional status was not provided. This bit is cleared by
writing a one to the MCLR bit in this register.
Writing a one to this bit clears the MPU status bits 7, 8, 9
and 10 (MLTO, MLOB, MLPE, and MLBE) in this
register.
LCSR Programming Model
. . .
R/W
11 10
MCLR MLBE
C R
0 PS 0 PS
16
9 8
MLPE MLOB
R R
0 PS 0 PS
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