Abort Switch Interrupt Control Register - Motorola MVME172 Programmer's Reference Manual

ABORT Switch Interrupt Control Register

The following table describes the ABORT switch interrupt logic in the
MC2 chip.
ADR/SIZ
BIT 7
NAME
OPER
R
RESET 0
IL2-IL0
ICLR
IEN
INT
ABS
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$FFF42040 (8 bits)
6 5 4
ABS INT IEN
R R R/W
0 PL 0 PL 0 PL
These three bits select the interrupt level for the ABORT
switch. Level 0 does not generate an interrupt.
Writing a logic 1 to this bit clears the abort interrupt (i.e.,
the INT bit in this register). This bit is always read as zero.
When this bit set high, the interrupt is enabled. The
interrupt is disabled when this bit is low.
When this bit is high, an interrupt is being generated for
the ABORT switch. Therefore the interrupt is level-
sensitive to the presence of the INT bit. The interrupt is at
the level programmed in IL2-IL0.
The ABORT switch status set to a one indicates that the
ABORT switch is pressed. When it is a zero, the switch is
inactive.
Programming Model
3 2 1
ICLR IL2 IL1
C R/W R/W
0 PL 0 PL 0 PL
3
0
IL0
R/W
0 PL
3-41