Scsi Interrupt Control Register - Motorola MVME162FX Programmer's Reference Manual

MC2 Chip
3

SCSI Interrupt Control Register

ADR/SIZ
BIT
NAME
OPER
RESET
3-38
Reserved for internal use only. (V7 is set to a 1
V7
indicating that the IP2 chip #1 is present.)
7 6
INT
R R R
0 0 R
IL2-IL0 Interrupt Level. These three bits select the interrupt
level for the SCSI processor. Level 0 does not
generate an interrupt.
IEN Interrupt Enable. When this bit is set high, the
interrupt is enabled. The interrupt is disabled when
this bit is low.
INT Interrupt Status. This status bit reflects the state of
the INT pin from the SCSI processor (qualified by
the IEN bit). When this bit is high, a SCSI processor
interrupt is being generated at the level
programmed in IL2-IL0. This status bit does not
need to be cleared, because it is level sensitive.
$FFF4202C (8 bits)
5 4 3
IEN
R/W R
0 PL 0
2 1 0
IL2 IL1 IL0
R/W R/W R/W
0 PL 0 PL 0 PL