Table of Contents
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MC2 chip/VMEchip2 redundancies
MC68060
bus master support for 82596CA
indivisible cycles
1-58
indivisible RMW memory accesses
MCECC
5-1
features
5-1
functional description
internal register memory map
introduction
5-1
specifications
5-3
MCECC chip Memory Controller ASIC
MCECC internal register memory map
memory map
MCECC internal register
Memory Base Address Registers, IP2 chip
4-19
Memory Configuration Register
memory maps
BBRAM configuration area
BBRAM, TOD clock
Ethernet LAN
1-38
IP2 chip devices
4-9
IP2 chip, all devices
IP2 chip, Control and Status Registers
1-29,
4-11
local bus
1-9
local bus, 200/300-Series
local bus, 400/500-Series
local I/O devices, 200/300-Series
local I/O devices, 400/500-Series
MC2 chip
1-27
MCECC internal registers
SCSI
1-39
time-of-day clock
1-42
VMEbus
1-46
VMEchip2 GCSR 1-26,
VMEchip2 LCSR 1-22,
Z85230 SCC register
memory map of the MC2 chip registers
memory mezzanine board serial number
Memory Size Registers, IP2 chip
http://www.mcg.mot.com/literature
1-5
memory space
3-4
1-58
memory space accesses, IP
microprocessor
MIEN 2-75, 2-97,
5-2
Miscellaneous Control Register
5-10
MK48T58 memory map
MPU
1-3
1-35
5-15
MPU TEA, cause unidentified
MVIP IndustryPack interfaces
1-41
MVME172
1-40
1-28
MVME172 Version Register
MVME712x transition boards
N
no address increment DMA transfers
1-10
non-ECC DRAM controller
1-12
non-privileged access cycles 2-34,
1-14
Non-Volatile RAM (NVRAM)
1-18
no-VMEbus option
NVRAM memory map
5-10
O
overflow counter 2-73,
overview, MVME172
2-104
2-22
P
1-37
P2 chip
3-8
parity checking
1-45
performance, MCECC
4-21
16-bit IP_a
4-47
32-bit IP_ab
4-48
8-bit IP_a
4-46
4-52
1-3
3-12
1-40
local bus time-out
1-51
off-board error
1-51
parity error
1-50
Status and DMA Interrupt Count
Register
2-63
Status Register
3-46
VMEchip2 and
2-52
features
1-3
functional description
1-5
introduction
1-1
3-5
1-5
1-40
2-74
1-1
1-2
3-5
5-2
2-99
1-51
1-4
3-35
1-2
2-12
2-37
1-3
N
D
E
X
IN-7
I
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