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DMA Control Register 1
The registers which control IP_c and IP_d are not used on the 200/300-
Series MVME172.
ADR/SIZ
BIT
7
NAME
DHALT
OPER
R/W
RESET
0 R
XXX
A_CH1,
C_CH1
WIDTH1-
WIDTH0
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$FFFBC024, $3C, $54, $6C (8 bits each)
6
5
4
0
DTBL
ADMA
R/W
R/W
R/W
0 R
0 R
0 R
This bit must remain cleared. If it is set to a one, the IP2
chip ASIC will not function correctly.
When A_CH1 is set to a zero, DMA request 0 from
Industry Pack b is associated with DMACb register set.
When it is set to a one, DMA request 1 from Industry Pack
a is associated with DMACb register set. When C_CH1 is
set to a zero, DMA request 0 from Industry Pack d is
associated with DMACd register set. When it is set to a
one, DMA request 1 from Industry Pack c is associated
with DMACd register set. Note that DMACa register set
is always associated with DMA request 0 from Industry
Pack a and DMACc register set is always associated with
DMA request 0 from Industry Pack c. Therefore these bit
positions are not defined for these two register sets. Refer
to the section on the Enable DMA Function for
information and restrictions on the operation of A_CH1
and C_CH1.
WIDTH bits specify the width of the IndustryPack
interface at position a or position a_b. The following table
defines the bit encoding. Note that these width control bits
are independent of the width control bits in the General
Control Registers. Also note that unlike the width control
Programming Model
3
2
1
WIDTH1
WIDTH0
A_CH1
or
C_CH1
R/W
R/W
R/W
0 R
0 R
0 R
0
4
XXX
R/W
0R
4-37
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