Introduction; Features - Motorola MVME172 Programmer's Reference Manual

Introduction

This chapter describes the ECC DRAM Controller ASIC (MCECC) used
on the memory mezzanine boards with ECC protection. The MCECC is
designed for the 200/300-Series MVME172 boards and is used in a set of
two, to provide the interface to a 144-bit wide DRAM memory system.
Note that the 400/500-Series MVME172 does not contain this chip.

Features

Allows 2-1-1-1 memory accesses (sustained) for burst writes
Allows 4-1-1-1 memory accesses (sustained) for burst reads (5-1-1-
1 with BERR on or when FSTRD is cleared)
Supports byte, two-byte, four-byte, and cache line read or write
transfers
Programmable base address for DRAM
Built-in refresh timer and refresh controller
ECC
– Single Bit Error Detect and Correct
– Software enabled Interrupt on Single Bit Error
– Address and Syndrome Register For Single Bit Error Logging
Support
– Double Bit Error Detect
– Software programmable Bus Error and/or Interrupt on Double
Bit Error
Programmable period automatic scrub operation
5MCECC
5
5-1