Chip Id Register; Chip Revision Register - Motorola MVME172 Programmer's Reference Manual

MCECC

Chip ID Register

5
ADR/SIZ
BIT
NAME
OPER
RESET

Chip Revision Register

ADR/SIZ
BIT
NAME
OPER
RESET
5-14
The Chip ID Register is hard-wired to a hexadecimal value of $81. The
MCECC can be given a software reset by writing a value of $0F to this
register. This write is terminated properly with TA*, and sets most internal
registers to their default (power-up) state. Writes of any value other than
$0F to this register are ignored; however, the MCECC always terminates
the cycles properly with TA*.
Difference from MEMC040: value = $80 for MEMC040;
value = $81 for MCECC.
1st $FFF43000/2nd $FFF43100 (8-bits)
31 30 29
CID7 CID6 CID5
R R R
X X X
The Chip Revision Register is hard-wired to reflect the revision level of the
MCECC ASIC. The current value of this register is $00. Writes to this
register are ignored; however, the MCECC pair always terminates the
cycles properly with TA*.
Difference from MEMC040: none between corresponding
revisions of the two parts.
1st $FFF43004/2nd $FFF43104 (8-bits)
31 30 29
REV7 REV6 REV5
R R R
X X X
28 27 26
CID4 CID3 CID2
R R R
X X X
28 27 26
REV4 REV3 REV2
R R R
X X X
Computer Group Literature Center Web Site
25 24
CID1 CID0
R R
X X
25 24
REV1 REV0
R R
X X