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IP2 Chip
4
4-38
bits in the General Control Registers, these width control
bits define the width of both the memory and I/O
interface.
WIDTH1
0
0
1
1
ADMA
Setting ADMA to a one will enable the address mode
DMA operation. Setting it to a zero will enable the
standard mode of DMA operation. Refer to the section on
the DMA Enable Function for information and
restrictions on the operation of the ADMA control bit.
DTBL
DMAC operates in the direct mode when this bit is low,
and it operates in the command chaining mode when this
bit is high.
DHALT
When this bit is high, DMA halts at the end of a command
when DMA is operating in the command chaining mode.
When this bit is low, DMA executes the next command in
the list. Software must be careful not to change the state
of bits 0 through 6 of this control register when the
DHALT bit is set.
WIDTH0
Assumed Data Bus Width
0
1
0
1
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32 bits
8 bits
16 bits
Reserved
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