Dmac Control Register 2 (Bits 8-15) - Motorola MVME172 Programmer's Reference Manual

DFAIR
DTBL
DEN
DHALT

DMAC Control Register 2 (bits 8-15)

ADR/SIZ
BIT
15
NAME INTE
OPER
R/W
RESET
0 PS
This portion of the control register is loaded by the processor or by the
DMAC when it loads the command word from the command packet.
Because this register is loaded from the command packet in the command
chaining mode, the descriptions here also apply to the control word in the
command packet.
D16
http://www.mcg.mot.com/literature
VMEbus.
3 Release when a BRx* signal is active on the
VMEbus or the time on timer has expired.
When this bit is high, the DMAC requester operates in the
fair mode. It waits until its request level is inactive before
requesting the VMEbus. When this bit is low, the DMAC
requester does not operate in the fair mode.
The DMAC operates in the direct mode when this bit is
low, and it operates in the command chaining mode when
this bit is high.
The DMAC is enabled when this bit is set high. This bit
always reads 0.
When this bit is high, the DMAC halts at the end of a
command when the DMAC is operating in the command
chaining mode. When this bit is low, the DMAC executes
the next command in the list.
$FFF40034 (8 bits [7 USED] of 32)
14 13 12
SNP
R/W
0 PS
When this bit is high, the DMAC executes D16 cycles on
the VMEbus. When this bit is low, the DMAC executes
D32/D64 cycles on the VMEbus.
LCSR Programming Model
11 10 9
VINC LINC TVME
R/W R/W R/W
0 PS 0 PS 0 PS
2
8
D16
R/W
0 PS
2-57