Local Bus Interrupter Status Register (Bits 16-23) - Motorola MVME172 Programmer's Reference Manual

Local Bus Interrupter Status Register (bits 16-23)

ADR/SIZ
BIT
23
NAME VIA
OPER R
RESET
0 PSL
This register is the local bus interrupter status register. When an interrupt
status bit is high, a local bus interrupt is being generated. When an interrupt
status bit is low, a local interrupt is not being generated. The interrupt
status bits are:
LM0
LM1
SIG0
SIG1
SIG2
SIG3
DMA
VIA
http://www.mcg.mot.com/literature
$FFF40068 (8 bits of 32)
22 21 20
DMA SIG3 SIG2
R R R
0 PSL 0 PSL 0 PSL
GCSR LM0 interrupt.
GCSR LM1 interrupt.
GCSR SIG0 interrupt.
GCSR SIG1 interrupt.
GCSR SIG2 interrupt.
GCSR SIG3 interrupt.
DMAC interrupt.
VMEbus interrupter acknowledge interrupt.
LCSR Programming Model
19 18 17
SIG1 SIG0 LM1
R R R
0 PSL 0 PSL 0 PSL
2
16
LM0
R
0 PSL
2-79