Table of Contents
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VMEbus requester, DMAC
VMEbus slave
2-9
VMEbus Slave
Address Modifier Select Register 1
Address Modifier Select Register 2
Address Translation Address Offset
Register 1
Address Translation Address Offset
Register 2
Address Translation Select Register 1
2-30
Address Translation Select Register 2
2-31
Ending Address Register 1
Ending Address Register 2
GCSR Group Address Register
map decoders
2-26
programming
2-26
Starting Address Register 1
Starting Address Register 2
Write Post and Snoop Control Register 1
2-35
Write Post and Snoop Control Register 2
2-32
VMEbus system controller, VMEchip2
VMEbus timer
2-18
VMEbus to local bus interface 1-9,
VMEchip2 ASIC
1-2
block diagram
2-5
Board Status/Control Register
functional blocks
2-4
GCSR programming model
ID Register
2-105
introduction
2-1
LM/SIG Register
2-105
local BERR*
1-49
memory map, LCSR Summary
periodic interrupt example
programming model
Revision Register
2-105
VMEchip2/MC2 chip redundancies
http://www.mcg.mot.com/literature
2-13
2-36
2-33
2-29
2-31
2-28
2-29
2-47
2-28
2-29
2-17
2-9
2-107
2-101
2-22
B-1
2-20
1-5
W
watchdog timer 1-3,
3-8
VMEchip2 2-14,
2-15
Watchdog Timer Control Register
VMEchip2
2-72
write post
2-34
buffer 2-6,
2-9
bus error interrupter
register
2-32
timer
2-7
write post enable 2-32, 2-35, 2-39, 2-43,
2-44,
2-50
write posting 2-6,
2-38
definition
2-6
enable
2-51
operations
2-9
write-protect feature
3-2
Z
Z85230 SCC interface
3-6
Z85230 SCC Register addresses
3-43
2-19
1-37
IN-11
I
N
D
E
X
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