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MLTO
MLPE
MLBE
MCLR
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When this bit is set, the MPU received a TEA and the
status indicated a local bus time-out. This bit is cleared by
a writing a one to the MCLR bit in this register. This bit is
used with the "No VMEbus Interface" option and is
duplicated in the VMEchip2 at address $FFF40048 bit 7.
When this bit is set, the MPU received a TEA and the
status indicated a parity error during a DRAM data
transfer. This bit is cleared by writing a one to the MCLR
bit in this register. This bit is used with the "No VMEbus
Interface" option and is duplicated in the VMEchip2 at
address $FFF40048 bit 9.
When this bit is set, the MPU received a TEA and
additional status was not provided. This bit is cleared by
writing a one to the MCLR bit in this register. This bit is
used with the "No VMEbus Interface" option and is
duplicated in the VMEchip2 at address $FFF40048 bit 10.
Writing a one to this bit clears the MPU status bits 8, 9 and
10 (MLTO, MLPE, and MLBE) in this register.
Programming Model
3-47
3
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