Scc Interrupt Control Register - Motorola MVME172 Programmer's Reference Manual

SCC Interrupt Control Register

ADR/SIZ
BIT
23
NAME
OPER
R
RESET 0
IL2-IL0
IEN
INT
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$FFF4201C (8 bits)
22 21 20
INT IEN
R R R/W
0 0 PL 0 PL
These three bits select the interrupt level for the SCC
controller. Level 0 does not generate an interrupt.
When this bit is set high, the interrupt is enabled. The
interrupt is disabled when this bit is low.
This bit reflects the state of the INT pin from either
Z85230 controller (qualified by the IEN bit). When this
bit is high, an SCC controller interrupt is being generated
at the level programmed in IL2-IL0. When the interrupt is
cleared in the Z85230, INT returns to zero. During the
interrupt acknowledge cycle, interrupts from the first
Z85230 have priority over those from the second Z85230.
Programming Model
19 18 17
IL2 IL1
R R/W R/W
0 0 PL 0 PL
3
16
IL0
R/W
0 PL
3-23