Xilinx RocketIO X User Manual page 203

RX User Clock2 (RXUSRCLK2) (ta-
ble) 134
114
PCB Design Requirements
120
AC and DC Coupling
Differential Trace Design
114
Power Conditioning
120
Termination
PCS Reset 90
90
PCS/PMA Power Down
Physical Coding Sublayer (PCS)
Physical Media Attachment (PMA)
PMA 85
Supported Modes, Standards, Serial
Speeds, Clock Relationships, and
Bus Widths (table) 85
Supported Standards, Speeds, Bus
Widths, and Frequencies for Ref-
erence Clocks 85
PMA Attribute
147
Bus Ports (table)
Bus Waveform (figure)
147
Programming Bus
PMA Clock Parameters (table)
123 124
PMA Initialization ,
PMARXLOCKSEL
104
Receiver Lock Control
PMARXLOCKSEL Definition (table)
Ports
28
BREFCLKNIN
28
BREFCLKPIN
28
CHBONDDONE
28
CHBONDI
28
CHBONDO
ENCHANSYNC 28
29
ENMCOMMAALIGN
29
ENPCOMMAALIGN
LOOPBACK 29
29
PMAINIT
29
PMAREGADDR
PMAREGDATAIN 29
29
PMAREGRW
29
PMAREGSTROBE
PMARXLOCK 29
29
PMARXLOCKSEL
29
POWERDOWN
REFCLK 29
29
REFCLK2
29
REFCLKBSEL
REFCLKSEL 29
RXBLOCKSYNC64B66BUSE
29
RXBUFSTATUS
RXCHARISCOMMA 29
30 51
RXCHARISK
,
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
RXCLKCORCNT
RXCOMMADET
RXCOMMADETUSE
RXDATA
118
RXDATAWIDTH
RXDEC64B66BUSE
RXDEC8B10BUSE
RXDESCRAM64B66BUSE
RXDISPERR
28 41
,
RXIGNOREBTF
28 41
,
RXINTDATAWIDTH
RXLOSSOFSYNC
30
RXN
RXNOTINTABLE
RXP 30
RXPOLARITY
RXREALIGN
RXRECCLK
RXRESET
148
RXRUNDISP
RXSLIDE
136
RXUSRCLK
RXUSRCLK2
TXBUFERR
TXBYPASS8B10B
104
TXCHARDISPMODE
TXCHARDISPVAL
TXCHARISK
TXDATA
TXDATAWIDTH
TXENC64B66BUSE
TXENC8B10BUSE
TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH
TXKERR
33
TXN
TXOUTCLK
33
TXP
TXPOLARITY
TXRESET
TXRUNDISP
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
Ports (table)
Power Control Descriptions (table)
Power Filtering Network for One Trans-
171
29 ceiver
Power Regulation and Filtering
30
30
30
30
30
30
30
30
30 51
,
30
30
30
30 51
,
30
31
31
31
31 51
,
31
31
31
31
32
32 48
,
32 48
,
32 49
,
32
32
32
33
33
33
33
33
33
33
33
33 49
,
33
34
34
28
90
171
www.xilinx.com
1-800-255-7778
R
103
Random Jitter (RJ)
Receive
105
Equalization
172
Termination
Termination (figure) 120
Receiver Lock Control
104
PMARXLOCKSEL
REFCLK/BREFCLK Selection Logic
Reference Clock Oscillator Interface
above 400 MHz (figure)
up to 400 MHz (figure)
Resets and Power Down 90
RocketIO transceiver
199
application notes
RocketIO X
Clock Descriptions (table)
Cores per Device Type (table)
Features 21
RocketIO X Transceiver
Basic Architecture and Capabilities
25
26
Block Diagram
92
Emphasis
Instantiations 28
25
Overview
Supported Primitives (table)
Three ways to configure
129
Timing Model
117
Routing Serial Traces
Running Disparity Control (table)
S
Serial Backplane System Design
Connector to PCB Launch
177
Transmission Lines
91
Serial I/O Description
Signal Values
for a Channel Bonding Skew (table)
68
for a Pointer Difference Status (table)
68
for Event Indication (table)
Simulation and Implementation
125
Simulation Models
125
HSPICE
125
SmartModels
Single-Ended Trace Geometry (figure)
118
Static Signals (Control Inputs)
Status and Event Bus 68
R
170
122
122
129
25
27
27
48
177
177
69
123
43
203