Xilinx RocketIO X User Manual page 33

Available Ports
Table 1-4: Primitive Ports (Continued)
Port
TXENC8B10BUSE
TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH[1:0]
TXKERR[7:0]
TXN
TXOUTCLK
TXP
TXPOLARITY
TXRESET
TXRUNDISP[7:0]
TXSCRAM64B66BUSE
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
I/O Port Size
I 1 If asserted High, the 8B/10B encoder is used. If deasserted,
the 8B/10Bencoder is bypassed.
I 1 If asserted High, the 64B/66B gearbox is used. If deasserted,
the 64/66 gearbox is bypassed.
TXSCRAM64B66USE = TXGEARBOX64B66BUSE
I 1 If asserted High, the TX differential pairs are forced to be a
constant 1/0. TXN = 1, TXP = 0
I 2 (00, 01, 10, 11) Indicates internal data width (see
page
(1)
O 1, 2, 4, 8 Indicates even boundary for bypassing in 64B/66B mode.
O 1 Transmit differential port (FPGA external)
O 1 Synthesized Clock from RocketIO X transmitter. This clock
can be scaled (e.g., for 64B/66B) relative to BREFCLK,
depending upon the specific operating mode of the
transmitter.
O 1 Transmit differential port (FPGA external)
I 1 Specifies whether or not to invert the final transmitter
output. Able to reverse the polarity on the TXN and TXP
lines. Deasserted sets regular polarity. Asserted reverses
polarity.
I 1 Synchronous TX system reset that "recenters" the transmit
elastic buffer. It also resets 8B/10B encoder and other
internal transmission registers. It does not reset the
transmission PLL.
(1)
O 1, 2, 4, 8 Signals the running disparity for its corresponding byte,
after that byte is encoded. Zero equals negative disparity
and positive disparity for a one. This is also overloaded to be
the data output bus of the PMA attribute bus. See
C, "PMA Attribute Programming Bus"
I 1 If asserted High, the 64B/66B scrambler is used. If
deasserted, the 64B/66B scrambler is bypassed.
TXSCRAM64B66USE = TXGEARBOX64B66BUSE
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Definition
46).
R
Table 2-4,
Appendix
33