Xilinx RocketIO X User Manual page 30

R
Table 1-4: Primitive Ports (Continued)
Port
RXCHARISK[7:0]
RXCLKCORCNT[2:0]
RXCOMMADET
RXCOMMADETUSE
RXDATA[63:0]
RXDATAWIDTH[1:0]
RXDEC64B66BUSE
RXDEC8B10BUSE
RXDESCRAM64B66BUSE
RXDISPERR[7:0]
RXIGNOREBTF
RXINTDATAWIDTH[1:0]
RXLOSSOFSYNC[1:0]
RXN
RXNOTINTABLE[7:0]
RXP
RXPOLARITY
30
I/O Port Size
(1)
O 1, 2, 4, 8 If 8B/10B decoding is enabled, it indicates that the received
data is a "K" character when asserted. Included in Byte-
mapping. If 8B/10B decoding is bypassed, it remains as the
first bit received (Bit "a") of the 10-bit encoded data (see
Figure
O 3 Status that denotes occurrence of clock correction, channel
bonding, and receive FIFO pointer status. This status is
synchronized on the incoming RXDATA. See
Correction," page 63
O 1 Indicates that the symbol defined by
PCOMMA_10B_VALUE (IF PCOMMA_DETECT is
asserted) and/or MCOMMA_10B_VALUE (if
MCOMMA_DETECT is asserted) has been received.
I 1 If asserted High, the comma detect is used. If deasserted, the
comma detect is bypassed.
(2)
O 8, 16, 32, 64 Up to eight bytes of decoded (8B/10B encoding) or encoded
(8B/10B bypassed) received data at the user fabric.
I 2 (00, 01, 10, 11) Indicates width of FPGA parallel bus. See
"Bus Interface" in Chapter
I 1 If asserted High, the 64/B66B decoder is used. If deasserted,
the 64/66 decoder is bypassed.
I 1 If asserted High, the 8B/10B decoder is used. If deasserted,
the 8b/10b decoder is bypassed.
CLK_COR_8B10B_DE = RXDEC8B10BUSE
I 1 If asserted High, the scrambler is used. If deasserted, the
scrambler is bypassed.
(1)
O 1, 2, 4, 8 If 8B/10B encoding is enabled it indicates whether a
disparity error has occurred on the serial line. Included in
Byte-mapping scheme.
I 1 If asserted High, the block type field (BTF) is ignored in the
64/66 decoder. Instead of reporting an error, the block is
passed on as is. If deasserted, unrecognized BTFs are
marked as error blocks.
I 2 (00, 01, 10, 11) Sets the internal mode of the receive PCS,
either 16, 20, 32, or 40 bit.
O 2 Bit 0 is always zero. Bit 1 indicates there is a 64B/66B Block
Lock when deasserted to logic Low.
I 1 Serial differential port (FPGA external)
(1)
O 1, 2, 4, 8 Status of encoded data when the data is not a valid character
when asserted High. Applies to the byte-mapping scheme.
I 1 Serial differential port (FPGA external)
I 1 Similar to TXPOLARITY, but for RXN and RXP. When
deasserted, assumes regular polarity. When asserted,
reverses polarity.
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Chapter 1: RocketIO X Transceiver Overview
Definition
2-3).
and "Status and Event Bus," page
2.
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
"Clock
68.