Xilinx RocketIO X User Manual page 31

Available Ports
Table 1-4: Primitive Ports (Continued)
Port
RXREALIGN
RXRECCLK
RXRESET
RXRUNDISP[7:0]
RXSLIDE
RXUSRCLK
RXUSRCLK2
TXBUFERR
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
I/O Port Size
O 1 Signal from the PMA denoting that the byte alignment with
the serial data stream changed due to a comma detection.
Asserted High when alignment occurs.
O 1 Clock recovered from the data stream and divided. Divide
ratio depends on PMA_SPEED setting and/or PMA
attributes. See
Bus."
I 1 Synchronous RX system reset that "recenters" the receive
elastic buffer. It also resets 8B/10B decoder, comma detect,
channel bonding, clock correction logic, and other internal
receive registers. It does not reset the receiver PLL.
(1)
O 1, 2, 4, 8 Signals the running disparity (0 = negative, 1 = positive) in
the received serial data. If 8B/10B encoding is bypassed, it
remains as the second bit received (Bit "b") of the 10-bit
encoded data.
I 1 Enables the "slip" of the detection block by 1 bit. To enable
a slide of 1 bit, it increments from a lower bit to a higher bit.
This signal must be asserted and then deasserted
synchronous to RXUSRCKLK2. RXSLIDE must be held Low
for at least two clock cycles before being asserted High
again.
I 1 Clock from a DCM or a BUFG that is used for reading the RX
elastic buffer. It also clocks CHBONDI and CHBONDO in
and out of the transceiver. Typically, the same as
TXUSRCLK.
Note:
phase from each other.
I 1 Clock output from a DCM that clocks the receiver data and
status between the transceiver and the FPGA fabric.
Typically, the same as TXUSRCLK2.
Note:
phase from each other.
O 1 Provides status of the transmission FIFO. If asserted High,
an overflow/underflow has occurred. When this bit
becomes set, it can only be reset by asserting TXRESET.
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Definition
Appendix C, "PMA Attribute Programming
RXUSRCLK and RXUSRCLK2 should be 180° out of
RXUSRCLK and RXUSRCLK2 should be 180° out of
R
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