Package To Pcb Launch - Xilinx RocketIO X User Manual

Package to PCB Launch

to an inner layer. This technique completely eliminates the via stub; however, it is often
difficult to design boards with multiple blind via depths.
A third and final way to reduce via stub effects is to route signals on the lower layers
within the backplane. Various combinations of these techniques can be used to improve
backplane performance. Regardless of the method, via stubs on the backplane should be
limited to 50 mil or less to ensure that the resonance point of the via gets pushed out past
10 GHz. Larger via stubs can be used, but they directly impact the backplane length that
can be achieved.
Not all signal layers require a unique solution. Signals running on routing layers that are
near each other might be able to share the same backdrill or blind via depth. Signals
running on the lower layers of the backplane do not need to be backdrilled if they are
already less than 50 mil from the bottom.
Antipad design can also have an effect on the performance of the backplane. The use of
rectangular antipads placed around each signal pair is recommended to reduce via
capacitance. Reducing via capacitance with larger antipads helps to limit the amount of
signal loss through the via. However, larger antipads can also produce additional crosstalk
between signal pairs. The balance between signal loss and crosstalk must be determined
based on the backplane application.
Crosstalk should also be considered when developing the backplane routing
configuration. Receiver input pairs should not be surrounded by transmitter output pairs
within the backplane connector. Routing a single transmit pair next to a single receive pair
is acceptable, but ideally the backplane should be designed so that all transmitter output
pairs are routed through one half of the connector, and all receiver input pairs are routed
through the other half of the connector. Careful attention should also be paid to where
grounding shields are located within the connector.
Alternative connector technologies should be considered for driving longer distances
across the backplane as well as reducing crosstalk within the connector. Surface mount
(SMT) connectors and compression-fit connectors are two examples. Backplanes designed
for these connector types can be further optimized to reduce overall via size, resulting in
less coupling between vias and less signal loss through the vias.
Package to PCB Launch
The MGT pins are located on the periphery of the Virtex-II Pro X device. It is
recommended that microstrip traces be used to route signals to and from MGT pins for a
short distance (a few millimeters) before routing them through differential vias to lower
signal layers. Differential stripline traces should be used for routing in inner layers.
Many of the design techniques used at the backplane connector can be used for optimizing
the launch from the package onto the PCB line card or switch card. Signals should be
routed on layers near the bottom of the board whenever possible. If signals are routed on
the upper layers of the board, backdrilling, blind vias, or buried vias should be used to
reduce stubs to less than 50 mil. Rectangular antipads should be utilized in a similar
fashion as discussed in the previous section. Finally, pads should be removed from all
unused signal layers.
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
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