Xilinx RocketIO X User Manual page 136

R
Table A-5: PMA Clock Parameters
Parameter
T _PADDR/T
GCCK GCCK
T _PINIT/T _PINIT
GCCK GCCK
T _PLKSEL/T
GCCK GCCK
T _PRW/T _PRW
GCCK GCCK
T _PSTRB/T _PSTRB
GCCK GCCK
T _PDAT/T _PDAT
GDCK GCCK
Notes:
1. See Appendix C, "PMA Attribute Programming Bus"
Table A-6: Miscellaneous Clock Parameters
Parameter
T
REFPWH
T
REFPWL
T
BREFNPWH
T
BREFPPWH
T
BREFNPWL
T
BREFPPWL
T
TXPWH
T
TXPWL
Notes:
1. REFCLK is not synchronous to any RocketIO X signals.
2. TXUSRCLK is not synchronous to any RocketIO X signals.
136
Function
_PADDR Control inputs
Control inputs
_PLKSEL Control inputs
Control inputs
Control inputs
Data inputs
for additional timing information.
Function
Clock pulse width, High state REFCLK(1)
Clock pulse width, Low state REFCLK(1)
Clock pulse width, High state BREFCLKNIN(1)
Clock pulse width, High state BREFCLKPIN(1)
Clock pulse width, Low state BREFCLKNIN(1)
Clock pulse width, Low state BREFCLKPIN(1)
Clock pulse width, High state TXUSRCLK
Clock pulse width, Low state TXUSRCLK
Appendix A: RocketIO X Transceiver Timing Model
PMAREGADDR[5:0]
PMAINIT
PMARXLOCKSEL
PMAREGRW
PMAREGSTROBE
PMAREGDATAIN[7:0]
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Signals
Signals
(2)
(2)
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004