Appendix G: Related Online Documents; Application Notes; Xapp752: Virtex-Ii Pro X Oc-48 Jitter Compliance Test Results; Xapp762: Rocketio X Bit-Error Rate Tester Reference Design - Xilinx RocketIO X User Manual

R
Related Online Documents
The documents described in this Appendix are accessible on the Xilinx website at
www.xilinx.com. Document links shown in blue are clickable in this PDF file, providing
easy access to the most current revision of each document.

Application Notes

XAPP752: Virtex-II Pro X OC-48 Jitter Compliance Test Results

This application note explains the results of the Virtex-II Pro X MGT tests against the
ITU/Bellcore GR-235 Specification for Jitter Tolerance, Jitter Transfer, and Jitter
Generation. The ITU/Bellcore GR-235 Specification has three jitter specifications that a
transceiver must meet to claim OC-48 jitter compliance. This compliance ensures that the
transceiver interoperates with any other transceiver that also meets these jitter
specifications and controls the accumulation of timing jitter within the connection to
acceptable levels.

XAPP762: RocketIO X Bit-Error Rate Tester Reference Design

This application note describes the implementation of a RocketIO™ X bit-error rate tester
(XBERT) reference design. The reference design generates and verifies non-encoded high-
speed serial data on one or multiple point-to-point links (2.5 Gb/s to 10 Gb/s) between
RocketIO X multi-gigabit transceiver (MGT) ports, embedded within a single Virtex-II
Pro™ X FPGA. This high-speed serial data is constructed in FPGA fabric using a pseudo-
random bit sequence (PRBS) pattern, a clock pattern, or a user-defined pattern. The
reference design provides access to the PMA attribute programming bus on the
RocketIO X MGT, which enables real-time control of PMA features, such as the TX output
swing, TX pre-emphasis, and RX equalization. The reference design utilizes the
UltraController™ embedded processor—a lightweight PowerPC™ microcontroller
solution. The embedded PPC405 processor transfers control and status between the XBERT
module and the UART core through the General-Purpose Input/Output (GPIO) interface
of the UltraController block, and enables a user interface through the software and an
external RS-232 serial port. The reference design is built using the Embedded Development
Kit (EDK), and it can be easily modified or extended.
XAPP767: RocketIO X Transceiver Clock Mode Switcher for
Virtex-II Pro X FPGAs
RocketIO™ X Multi-Gigabit Transceivers (MGTs) operating at 10.3125 Gb/s offer great
flexibility, providing programmability of serial rates, datapath widths, encoding schemes,
and reference clock to serial rate ratios (multipliers). Most of these options are modified by
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
www.xilinx.com
1-800-255-7778
Appendix G
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