Xilinx RocketIO X User Manual page 34

R
Table 1-4: Primitive Ports (Continued)
Port
TXUSRCLK
TXUSRCLK2
Notes:
1. Port size depends on which primitive is used (1, 2, 4, 8 byte).
2. Port size depends on which primitive is used (8, 16, 32, 64 byte).
34
I/O Port Size
I 1 Clock output from a DCM that is clocked with the REFCLK
(or other reference clock). This clock is used for writing the
TX buffer and is frequency-locked to the REFCLK.
Note:
from each other.
I 1 Clock output from a DCM that clocks transmission data and
status and reconfiguration data between the transceiver an
the FPGA fabric. The ratio between the TXUSRCLK and
TXUSRCLK2 depends on the width of the TXDATA.
Note:
from each other.
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Chapter 1: RocketIO X Transceiver Overview
Definition
TXUSRCLK and TXUSRCLK2 should be 180° out of phase
TXUSRCLK and TXUSRCLK2 should be 180° out of phase
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004