Xilinx RocketIO X User Manual page 29

Available Ports
Table 1-4: Primitive Ports (Continued)
Port
ENMCOMMAALIGN
ENPCOMMAALIGN
LOOPBACK[1:0]
PMAINIT
PMAREGADDR[5:0]
PMAREGDATAIN[7:0]
PMAREGRW
PMAREGSTROBE
PMARXLOCK
PMARXLOCKSEL[1:0]
POWERDOWN
REFCLK
REFCLK2
REFCLKBSEL
REFCLKSEL
RXBUFSTATUS[1:0]
RXBLOCKSYNC64B66BUSE
RXCHARISCOMMA[7:0]
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
I/O Port Size
I 1 Selects realignment of incoming serial bitstream on minus-
comma. When asserted realigns serial bitstream byte
boundary to where minus-comma is detected.
I 1 Selects realignment of incoming serial bitstream on plus-
comma. When reasserted realigns serial bitstream byte
boundary to where plus-comma is detected.
I 2 Selects the three loopback test modes. These modes are
internal parallel, pre-driver serial, and post-driver serial.
See
I 1 When asserted High and then deasserted Low, reloads the
PMA coefficients into the PMA from the attribute
PMA_SPEED and then resets the PCS.
I 6 PMA attribute bus address. This input is asynchronous.
I 8 PMA attribute bus data input. This input is asynchronous.
I 1 PMA attribute bus read/write control. This input is
asynchronous.
I 1 PMA attribute bus strobe. Note: This input is asynchronous.
O 1 Indicates that the receive PLL has locked in the fine loop.
When RX PLL is set to "Lock to Data," this signal is always
a logic 1.
I 2 Selects determination of lock in the receive PLL. See
Table 4-8, page
I 1 Shuts down both the receiver and transmitter sides of the
transceiver when asserted High. Note: This input is
asynchronous.
I 1 The reference clock net that is embedded within the fabric.
I 1 An alternative to REFCLK. Can be selected by the
REFCLKSEL.
I 1 Selects between BREFCLK and REFCLK/REFCLK2 as
reference clock. Asserted selects BREFCLK. Deasserted
selects REFCLK or REFCLK2, depending on REFCLKSEL.
I 1 Selects between REFCLK or REFCLK2 as reference clock.
Deasserted selects REFCLK. Asserted selects REFCLK2.
O 2 Receiver elastic buffer status. Indicates the status of the
receive FIFO pointers, channel bonding skew, and clock
correction events. See
I 1 If asserted, the block sync is used. If deasserted, the block
sync logic is bypassed.
(1)
O 1, 2, 4, 8 Indicates the reception of K28.0, K28.5, K28.7, and some out
of band commas (depending on the setting of
DEC_VALID_COMMA_ONLY by the 8B/10B decoder.
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Definition
Table 5-3, page 127 for more information.)
104.
"Status and Event Bus," page
R
68.
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