Figure D-1: Refclk/Brefclk Selection Logic; Table D-2: Brefclk Inputs; Table D-3: Virtex-Ii Pro X Brefclk Pin Numbers - Xilinx RocketIO X User Manual

R

Table D-2: BREFCLK Inputs

Figure D-1
and REFCLKBSEL.
Although the BREFCLK2 pins from Virtex-II Pro FPGA are still available as global clock
resources, they do not support a dedicated, low-jitter reference clock to the Virtex-II Pro X
MGTs.
Table D-3
compatible with corresponding Virtex-II Pro package pins. Note that these pads must be
used for BREFCLK operations.

Table D-3: Virtex-II Pro X BREFCLK Pin Numbers

The Virtex-II Pro X BREFCLK inputs are LVDS compatible with on-chip, 100Ω differential
termination. Reference oscillators similar to the ones used with Virtex-II Pro FPGAs can be
used with Virtex-II Pro X FPGAs. These include the Epson EG2121CA and EG2101CA
series, which support the full range of BREFCLK frequencies (up to 645 MHz). For more
information, see the reference clock sections of this guide and the RocketIO Transceiver User
Guide (
170
Appendix D: Virtex-II Pro to Virtex-II Pro X FPGA Design Migration
Top
P GCLK4S
N GCLK5P
shows how REFCLK and BREFCLK are selected through use of REFCLKSEL
REFCLKBSEL
refclk
refclk2
REFCLKSEL
brefclkp
brefclkn

Figure D-1: REFCLK/BREFCLK Selection Logic

shows the BREFCLK pin numbers for Virtex-II Pro X packages. These are
Package
FF896
FF1704
).
UG024
www.xilinx.com
1-800-255-7778
BREFCLK
P
N
0
1.5V
1
0
to PCS and PMA
1
2.5V
BREFCLK Pin Numbers
Top (P/N)
F16/G16
G22/F22
Bottom
GCLK6P
GCLK7S
refclk_out
ug035_apD_01_090903
Bottom (P/N)
AH16/AJ16
AU22/AT22
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004