Xilinx RocketIO X User Manual page 32

R
Table 1-4: Primitive Ports (Continued)
Port
TXBYPASS8B10B[7:0]
TXCHARDISPMODE[7:0]
TXCHARDISPVAL[7:0]
TXCHARISK[7:0]
TXDATA[63:0]
TXDATAWIDTH[1:0]
TXENC64B66BUSE
32
I/O Port Size
I 8 If TXENC8B10BUSE = 1 and TXENC64B66BUSE = 0
(8B/10B encoder enabled and 64B/66B encoder disabled),
each bit of TXBYPASS8B10B[7:0] controls the bypass of the
corresponding TXDATA byte; an asserted bit bypasses
encoding for the data in the corresponding byte lane.
If TXENC8B10BUSE = 0 and TXENC64B66BUSE = 1
(8B/10B encoder disabled and 64B/66B encoder enabled),
TXBYPASS8B10B[2:0] bits are used for additional 64B / 66B
encoder block bypass control. TXBYPASS8B10B[7:3] bits are
not relevant in this particular configuration. Bits [2:1] carry
the substitute sync header (SH[1:0]) for the block bypass
operation; bit [0] is asserted for each block that the user
wants to bypass.
(1)
I 1, 2, 4, 8 If 8B/10B encoding is enabled, this bus determines what
mode of disparity is to be sent. When 8B/10B is bypassed,
this becomes the first bit transmitted (Bit "a") of the 10-bit
encoded TXDATA bus section (see
each byte specified by the byte-mapping. The bits have no
meaning if TXENC8B10BUSE is deasserted.
(1)
I 1, 2, 4, 8 If 8B/10B encoding is enabled, this bus determines what
type of disparity is to be sent. When 8B/10B is bypassed,
this becomes the second bit transmitted (Bit "b") of the 10-
bit encoded TXDATA bus section (see
each byte specified by the byte-mapping section. The bits
have no meaning if TXENC8B10BUSE is deasserted.
(1)
I 1, 2, 4, 8 If TXENC8B10BUSE = 1 (8B/10B encoder enable), then
TXCHARISK[7:0] signals the K-definition of the TXDATA
byte in the corresponding byte lane. (1 indicates that the
byte is a K character; 0 indicates that the byte is a data
character)
If TXENC64B66BUSE = 1 (64B/66B encoder enable), then
TXCHARISK[3:0] signals the block-formatting definitions
of TXDATA (1 indicates that the byte is a control character;
0 indicates that the byte is a data character).
TXCHARISK[7:4] bits are not relevant in this particular
configuration.
(2)
I 8, 16, 32, 64 Transmit data from the FPGA user fabric that can be 1, 2, 4,
or 8 bytes wide, depending on the primitive used.
TXDATA[7:0] is always the first byte transmitted. The
position of the first byte depends on selected TX data path
width.
I 2 (00, 01, 10, 11) Indicates width of FPGA parallel bus. See
"Bus Interface" in Chapter
I 1 If asserted High, the 64B/66B encoder is used. If deasserted,
the 64/66 encoder is bypassed.
www.xilinx.com
1-800-255-7778
Chapter 1: RocketIO X Transceiver Overview
Definition
Table 2-6, page
Table 2-6, page
2.
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
49) for
49) for