Intel EP80579 Manual page 296

Schematics Checklist—Intel
Table 100. Schematic Checklist (Sheet 13 of 26)
Checklist Items
SIU_RXD[2:1]
SIU_TXD[2:1]
UART_CLK
SATA_TXp[1:0],
SATA_TXn[1:0],
SATA_RXp[1:0],
SATA_RXn[1:0]
SATA_RBIAS
SATA_RBIAS#
SATA_CLKREFp,
SATA_CLKREFn
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
I/O Type
Recommendations
(Default)
• Connect signals appropriately
I/O
to RS-232 Transceiver
• Connect signals appropriately
to RS-232 Transceiver
Strapping Options:
(GPIO IRQ Capability Strap)
• 0 = GPIO IRQ Capability
enabled
I/O
• 1 = GPIO IRQ Capability
disabled
Note: (default = 0) Connect
SIU_TXD[2] through a 510
Ω pull-down resistor to
ground to enable IRQ
capability
• Connect to 48 MHz clock
(USB_48) from the CK410
Clock Synthesizer
I
• Connect clock through a 33 Ω
±5% series resistor.
Serial ATA (SATA) Interface
Requires series AC coupling
capacitors:
• Connect 0.01µF ±10%
I/O
capacitor on each data line
between EP80579 and SATA
connector.
SATA Bias Resistor
• Short signals SATA_RBIAS to
SATA_RBIAS# at package.
I
• Pull down shorted signal
through a 24.9 Ω ±1% resistor to
ground .
• Connect to SRC_4_SATAp/n
(100 MHz) clock outputs of the
CK410 Clock Synthesizer.
I • Connect clocks through 33 Ω
±5% series resistors
• Connect clocks through 49.9 Ω ±1%
resistors to ground
• UART Port[2:1]Serial Data Input:
Note:
• Must be pulled high through a 10
• UART Port[2:1] Serial Data Output:
SIU_TXD[2] -
• Signals have 50KΩ internal pull-ups
Note:
• SIU_TXD[2] needs to be strapped
• SIU_TXD[1] can be left as no
Note:
• Both UART_CLK and USB_CLK
• Isolate UART_CLK from USB_CLK
• Connect UART_CLK to a 48 MHz
• See
Note:
If a SATA port is not used or connected
to an interfacing device, terminate the
signals as follows:
• SATA_RXp/SATA_RXn, SATA_TXp/
Note:
• Tie SATA_RBIAS and SATA_RBIAS#
Note:
• Connect SATA_CLKREFp/
• See
Comments
Serial data input form external
devices to the receive UART port
[2:1].
KΩ resistor when the port is not
connected to an interfacing device
Serial data output to the
communication peripheral/modem
or data set for UART port [2:1].
Upon reset, the TXD pins will be set
to MARKING condition (logic '1'
state).
appropriately even if the port is not
used or not connected to an
interfacing device.
connect (NC) if the port is not used.
(CLK48) use the same clock output
(USB_48) from the CK410 Clock
Synthesizer.
(CLK48) through 33 Ω ±5% series
resistors
clock source even when the SIU
ports are not connected to any
interfacing device.
Section 2.3
SATA_TXn signals may be left as no
connect (NC)
together and connect to GND
through a 24.9 Ω ±1% resistor even
when the SATA port is not used or
connected to an interfacing device.
SATA_CLKREFn to a 100 MHz clock
source even if the SATA port is not
used or connected to an interfacing
device.
Section 2.3
May 2010
296