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12.0
Universal Serial Bus (USB) Interface
12.1
USB Interface
The EP80579 contains one Enhanced Host Controller Interface (EHCI) USB 2.0 and one
Universal Host Controller Interface (UHCI). The EP80579 supports a maximum of two
USB ports, which can be configured independtly as either EHCI or UHCI. The
connection to either a UHCI or the EHCI port is dynamic and dependent on the USB
device capability, meaning that all ports support high-speed, full-speed, and low-speed
USB devices.
The USB ports support a debug port at USB 2.0 transfer rates and also support wakeup
from sleeping states S3 and S5. The USB 2.0 interfaces can be configured as master
only.
12.2
Layout Guidelines
12.2.1
General Routing and Placement
Use the following general routing and placement guidelines when laying out a new
design to help maximize signal quality and minimize EMI problems:
• Place EP80579 and major components on the un-routed board first. With minimum
trace lengths, route high-speed clock, periodic signals, and USB 2.0 differential
pairs first. Maintain the maximum possible distance between high-speed clocks/
periodic signals to USB 2.0 differential pairs and any connector leaving the PCB
(i.e., I/O connectors, control and signal headers, or power connectors).
• Ensure the USB 2.0 signals are ground referenced. Based on recommended stack-
up, this would mean signals routed on signal layer 3 and 8.
• Route USB 2.0 signals using a minimum number of vias and corners. This reduces
reflections and impedance changes.
• When a 90° turn becomes necessary, use two 45° turns or an arc instead of making
a single 90° turn. This reduces reflections on the signal by minimizing impedance
discontinuities.
• Do not route USB 2.0 traces under crystals, oscillators, clock synthesizers,
magnetic devices, or ICs that use and/or duplicate clocks.
• Avoid stubs on high-speed USB signals, as stubs will cause signal reflections and
affect signal quality. If a stub is unavoidable in the design, the total of all the stubs
on a particular line must not be greater than 200 mils.
• Route all traces over continuous planes, with no interruptions. Avoid crossing over
an anti-etch, plane split if possible. Crossing over anti-etch, plane splits, increases
inductance and radiation levels by forcing a greater loop area. Likewise, avoid
changing layers with USB 2.0 traces as much as practical. Changing layers to avoid
crossing a plane split is preferable. See
Outs (Anti-Etch)" on page 170
• Separate signal traces into similar categories and route similar signal traces
together, such as routing differential pairs together.
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
164
®
Intel
EP80579 Integrated Processor Product Line—Universal Serial Bus (USB) Interface
Section 12.3, "Plane Splits, Voids, and Cut-
for further details.
May 2010
Order Number: 320068-005US
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