Chip Select Topologies; Multi-Drop Topology Diagram; Multi-Drop Topology Trace Lengths For The Development Board - Intel EP80579 Manual

Figure 146. Multi-drop Topology Diagram
EP80579
EX_CS7#
EX_CS6#
EX_CS5#
EX_CS4#
EX_CS3#
EX_CS2#
EX_CS1#
EX_CS0#
EX_DATA L1
EX_ADDR L1
EX_RD# L1
EX_WR# L1
STRATA
FLASH #1
Table 88 contains information for trace length measurements that came from the
Development Board. Use this information as a reference when designing similar
topologies. It is strongly recommended to perform simulations for your specific
applications.
Table 88.

Multi-drop Topology Trace Lengths for the Development Board

Trace
L1
L2
L3
L4
L5
L6
L7
L8
22.3.2

Chip Select Topologies

Chip Select is a point-to-point signal that must be closely routed to match the Address,
Data, and Control signal trace lengths. In order for signals to arrive at the same time
through the bus and avoid timing issues, all three groups must tightly match to
+/- 500 mil.
External board pull-ups are required on EX_CS_N to ensure the signal remains
deasserted, so that a spurious transfer does not start due to board noise. Additionally,
the system designer is responsible for ensuring that all the tri-stated signals do not
become indeterminate. It is recommended to terminate the EX_CS_N signal with a 10K
ohm pull-up resistor.
®
Intel EP80579 Integrated Processor Product Line
Platform Design Guide
239
®
Intel EP80579 Integrated Processor Product Line—Local Expansion Bus (LEB) Interface
EX_CS[7:0]#
L2 L3 L4
L2 L3 L4
L2 L3 L4
L2 L3 L4
STRATA COMPACT
FPGA
FLASH #2
Average
Length
2.5 inch
1.0 inch
2.5 inch
2.0 inch
1.0 inch
1.5 inch
1.0 inch
5.0inch
BUFFER
L5 L6
L5 L6
L5 L6
L5 L6
FLASH
L7 L8
L7 L8
L7 L8
L7 L8
MEZZ
MEZZ MEZZ
#2
#1 #3
May 2010
Order Number: 320068-005US