Intel EP80579 Manual page 286

Schematics Checklist—Intel
Table 100. Schematic Checklist (Sheet 3 of 26)
Checklist Items
IERR#
IMCH Reset
RSTIN#
PWRGD
DDR2 SDRAM
DDR_DQ[63:0],
DDR_ECC[7:0],
DDR_DM[8:0],
DDR_DQS[8:0],
DDR_ DQS[8:0]#
DDR_A[14:0]
DDR_BA[2:0]
DDR_RAS#
DDR_CAS#
DDR_WE#
DDR_CS[1:0]#,
DDR_CKE[1:0],
DDR_ODT[1:0]
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
I/O Type
Recommendations
(Default)
• Connect to GPIO[40] to be
used as IOAPIC IRQ35
• Pull-up to EP80579 3.3V
O (VCC33) power supply using
10KΩ ± 5% if used.
• Can monitor signal using an
LED
Integrated Memory Controller Hub (IMCH) Interface
• Connects to EP80579 PLTRST#
I
output
• Connects to Platform
I
SYS_PWR_OK
• Directly connect from EP80579
to each DIMM with no
termination.
• For 32-bit mode, all unused
I/O
EP80579 DDR2 Data Bus
Interface Signals should be
pulled high to 1.8V
with 10KΩ pull-up resistors
• Connect to each DIMM
• Use 18 pF 5% 50V
compensation capacitor on
each signal.
O
• Use 60 Ω ±1%, 0.25W, pull-up
resistor to DDR Termination
voltage (DDR2_VTT) on each
signal.
• Use 60 Ω ±1%, 0.25W, pull-up
resistor to DDR Termination
voltage (DDR2_VTT) on each
signal.
• Connect DDR_CS[0]#/
DDR_CKE[0]/DDR_ODT[0] to
DIMM0 Rank 0
O
• Connect DDR_CS[1]#/
DDR_CKE[1]/DDR_ODT[1] to
DIMM0 Rank 1
• Connect DDR_CS[1]#/
DDR_CKE[1]/DDR_ODT[1] to
DIMM1 Rank 0
Comments
IERR# (EP80579 Internal Error) is
asserted by the IA-32 core as a result of
an internal error. Assertion of IERR# is
usually accompanied by a SHUTDOWN
transaction on the FSB. This transaction
may optionally be converted to an
external error signal (for example, NMI)
by EP80579. The IA-32 core keeps
IERR# asserted until the assertion of
INIT33V_OUT# or EP80579 is reset
using SYS_RESET#.
Note:
• This signal can be left as a no
connect (NC) if not used.
• This signal can be exposed via a
testpoint for debug purposes if not
used.
• 50KΩ internal pull-up.
• See Figure 75
( VCC18)
• Use one capacitor per signal to
DIMM0 only
• Place capacitor as close as possible
to DIMM0
• See Figure 82
• DIMM0 supports both single and
dual rank memory modules
• DIMM1 supports only single rank
memory modules
• See Figure 81
May 2010
286