Intel E6600 - Core 2 Duo Dual-Core Processor Specification
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Intel E6600 - Core 2 Duo Dual-Core Processor Specification

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®
Intel
Core
Δ
X6800
and Intel
Desktop Processor E6000
Δ
E4000
Sequence
Specification Update
— on 65 nm Process in the 775-land LGA Package supporting
®
Φ
Intel
64
Architecture, Intel
®
Intel
Trusted Execution Technologyŧ
December 2010
Notice: The Intel
contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are documented in
this Specification Update.
™
2 Extreme Processor
®
®
TM
Core
2 Extreme and Intel
®
™
Core
2 Duo
Virtualization Technology± and
®
TM
Core
2 Duo desktop processor may
Document Number:
Δ
and
313279-027

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Summary of Contents for Intel E6600 - Core 2 Duo Dual-Core Processor

  • Page 1 ® ® Notice: The Intel Core 2 Extreme and Intel Core 2 Duo desktop processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
  • Page 2 2 Extreme Processors may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. ®...

  • Page 3: Table Of Contents

    Component Identification Information ..................20 Errata ..........................23 Specification Changes ......................69 Specification Clarifications ....................70 Documentation Changes ...................... 71 § ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...

  • Page 4: Revision History

    Revision History Revision Description Date ® ® • Initial release of the Intel Core™2 Extreme Processor X6800 and Intel July 2006 -001 Core™2 Duo Desktop Processor E6000 Sequence Specification Update Out of Cycle • Updated Erratum AI19, AI29 and AI40...
  • Page 5 • Added processor number E4700 information Mar 3 2008 -026 • Added Erratum AI127, AI128 May 2008 December 8th, -027 • Added Erratum AI129 2010 ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...

  • Page 6: Preface

    This document may also contain information that has not been previously published. Affected Documents Document Title Document Number Intel ® Core™2 Extreme Processor X6800 and Intel ® Core™2 Duo 313278-008 Desktop Processor E6000 and E4000 Sequence Datasheet Related Documents Document Title Document Location ®...
  • Page 7 (datasheets, manuals, etc.). § ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...

  • Page 8: Summary Tables Of Changes

    The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
  • Page 9 Summary Tables of Changes Item Numbering Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor specification updates: ® ® Dual-Core Intel Xeon processor 7000 sequence ®...
  • Page 10 Summary Tables of Changes ® ® AK = Intel Core™2 Extreme quad-core processor QX6000 sequence and Intel Core™2 Quad processor Q6 00 sequence ® ® AL = Dual-Core Intel Xeon processor 7100 series ® ® AM = Intel Celeron processor 400 sequence ®...
  • Page 11 (E)CX May Get Incorrectly Updated When Performing Fast AI30 Fixed String REP MOVS or Fast String REP STOS With Large Data Structures ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 12 AI51 No Fix Taken after MOV SS/POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 13 PEBS Buffer Overflow Status Will Not be Indicated Unless AI72 Fixed IA32_DEBUGCTL[12] is Set The BS Flag in DR6 May be Set for Non-Single-Step #DB AI73 No Fix Exception ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 14 Not Count Some Decoded Instructions The Stack Size May be Incorrect as a Result of VIP/VIF Check AI95 Fixed on SYSEXIT and SYSRET ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 15 VMCALL failure due to corrupt MSEG location may cause VM AI108 Fixed Exit to load the machine state incorrectly ® Overlap of an Intel VT APIC Access Page in a Guest with the AI109 Fixed DS Save Area May Lead to Unpredictable Behavior...
  • Page 16 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Number DOCUMENTATION CHANGES There are no Documentation Changes in this Specification Update revision. § ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...

  • Page 17: Identification Information

    Identification Information Identification Information ® Figure 1. Intel Core™2 Duo Desktop Processor 2M SKU Package with 800 MHz FSB INTEL ©'05 E4500 INTEL® CORE™2 DUO SLxxx [COO] 2.20GHZ/2M/800/06 [FPO] ATPO ® Figure 2. Intel Core™2 Duo Desktop Processor 2M SKU Package with 1066 MHz FSB INTEL ©'05...
  • Page 18 Identification Information ® Figure 3. Intel Core™2 Duo Desktop Processor 4M SKU Package with 1066 MHz FSB INTEL ©'05 INTEL® CORE™2 DUO 6700 SLxxx [COO] 2.66GHZ/4M/1066/06 [FPO] ATPO ® Figure 4. Intel Core™2 Duo Desktop Processor 4M SKU Package with 1333 MHz FSB INTEL ©'05 E6850...
  • Page 19 Identification Information ® Figure 5. Intel Core™2 Extreme Processor Package INTEL ©'05 INTEL® CORE™2 EXTREME 6800 SLxxx [COO] 2.93GHZ/4M/1066/05B [FPO] ATPO § ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...

  • Page 20: Component Identification Information

    Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register. Refer to the Intel Processor Identification and the CPUID Instruction Application Note (AP-485) Conroe and Woodcrest Processor Family BIOS Writer’s Guide (BWG)
  • Page 21 Component Identification Information ® Table 1. Intel Core™2 Duo Desktop Processor 2M SKU Identification Information L2 Cache Core Processor Processor Speed S-Spec Size Package Notes Stepping Signature Number Core/Bus (bytes) 1.86 GHz / 1, 3, 4, 6, 7, 8, 9,...
  • Page 22 Component Identification Information ® Table 2. Intel Core™2 Duo Desktop Processor 4M SKU Identification Information L2 Cache Core Processor Processor Speed S-Spec Size Package Notes Stepping Signature Number Core/Bus (bytes) 2.33 GHz / 1, 3, 4, 6, 7, 8, 9, 10,...

  • Page 23: Errata

    DEFER# is received during a snoop phase and the Locked transaction is pipelined on the front side bus (FSB), LOCK# may unexpectedly de-assert. Implication: When this erratum occurs, the system may hang during shutdown. Intel has not observed this erratum with any commercially available systems or software.
  • Page 24 RFLAGS.RF bit will be unconditionally cleared after execution of the SYSRET instruction. Implication: The SYSRET instruction can not be used if the RF flag needs to be set after returning from a system call. Intel has not observed this erratum with any commercially available software. ®...
  • Page 25 #GP fault (general protection exception). Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software. Workaround: None Identified.
  • Page 26 Workaround: In the ACPI/OS implement a workaround by temporarily disabling the DTS threshold interrupt before updating the DTS threshold value. ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
  • Page 27 HLT or MWAIT events, are also not counted: a) RSM from a C-state SMI during an MWAIT instruction. b) RSM from an SMI during a HLT instruction. ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
  • Page 28 Software which is written so that multiple agents can modify the same shared Problem: unaligned memory location at the same time may experience a memory ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
  • Page 29 0x0. Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software, or system.
  • Page 30 The result of fetching code at that address is unpredictable and may include an unexpected trap or fault, or execution of the instructions found there. ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
  • Page 31 AI23. VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field ® Processors supporting Intel Virtualization Technology can execute VMCALL Problem: from within the Virtual Machine Monitor (VMM) to activate dual-monitor treatment of SMIs and SMM. Due to this erratum, if reserved bits are set to values inconsistent with VMX Capability MSRs, VMCALL may not VMFail.
  • Page 32 4G limit (0ffffffffh) may not signal a #GP fault. Implication: When such memory accesses occur in 32-bit mode, the system may not issue a #GP fault. ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
  • Page 33 Implication: (E)CX may contain an incorrect count which may cause some of the MOVS or STOS operations to re-execute. Intel has not observed this erratum with any commercially available software. Workaround: Do not use values in (E)CX that when multiplied by the data size give values larger than the address space size (64K for 16-bit address size and 4G for 32-bit address size).
  • Page 34 Software using unsynchronized XMC to modify the instruction byte stream of a processor can see unexpected or unpredictable execution behavior from the processor that is executing the modified code. ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
  • Page 35 Errata Implication: In this case, the phrase "unexpected or unpredictable execution behavior" encompasses the generation of most of the exceptions listed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide, including a General Protection Fault (GPF) or other unexpected behaviors.
  • Page 36 Workaround: Avoid segment base mis-alignment and address wrap-around at the segment boundary. For the steppings affected, see the Summary Tables of Changes. Status: ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
  • Page 37 Bit 31 of the FPU Data (Operand) Pointer is set. • • An FXSAVE instruction is executed Implication: Software depending on the full FPU Data (Operand) Pointer may behave unpredictably. ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 38 Shutdown Condition May Disable Non-Bootstrap Processors When a logical processor encounters an error resulting in shutdown, non- Problem: bootstrap processors in the package may be unexpectedly disabled. ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
  • Page 39 (e.g. NMI (Non-Maskable Interrupt), Debug break (#DB), Machine Check (#MC), etc.) Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially available software. Workaround: None Identified.
  • Page 40 Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any exception. Intel has not observed this erratum with any commercially available software, or system.
  • Page 41 An I/O read that redirects to MWAIT • ® • In systems supporting Intel Virtualization Technology a fault in the middle of an IO operation that causes a VM Exit Implication: SMM handlers may get false IO_SMI indication. Workaround: The SMM handler has to evaluate the saved context to determine if the SMI was triggered by an instruction that read from an I/O port.
  • Page 42 Implication: This erratum may lead to livelock, shutdown or other unexpected processor behavior. Intel has not observed this erratum with any commercially available system. Workaround: None Identified.
  • Page 43 , repeat string operations CMPSB, LODSB or SCASB may terminate without completing the last iteration. Intel has not observed this erratum with any commercially available software. Workaround: Do not use repeated string operations with RCX greater than or equal to 2 For the steppings affected, see the Summary Tables of Changes.
  • Page 44 Present or from Read/Write to Read Only, etc. Another processor, without corresponding synchronization and TLB flush, must • cause the permission change. ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 45 EFLAGS register on the page fault handler’s stack prematurely contains the final arithmetic flag values although the instruction has not yet completed. Intel has not identified any operating systems that inspect the arithmetic portion of the EFLAGS register during a page fault nor observed this erratum in laboratory testing of software applications.
  • Page 46 Workaround: Workaround: Software should not generate misaligned stack frames for use with IRET. For the steppings affected, see the Summary Tables of Changes. Status: ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
  • Page 47 Workaround: Do not use performance monitoring counters for precise event sampling when the precise event is dependent on the CPL value. For the steppings affected, see the Summary Tables of Changes. Status: ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
  • Page 48 If an asynchronous machine check occurs during an interrupt, call through Problem: gate, FAR RET or IRET and in the presence of certain internal conditions, ESP may be corrupted. ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...

  • Page 49: Software Interrupts

    Debug-Exceptions Field of the Guest State Area will be Incorrectly Set by VM Exit on a MOV to CR8 Instruction ® In a system supporting Intel Virtualization Technology, the BS bit (bit 14 of Problem: the Pending-Debug-Exceptions field) in the guest state area will be incorrectly set when all of the following conditions occur: The processor is running in VMX non-root as a 64 bit mode guest;...
  • Page 50 Workaround: None Identified. For the steppings affected, see the Summary Tables of Changes. Status: ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 51 16 bit operand size (REX.W =0 and 66H prefix) will only store 16 bits and leave bits 63:16 at the destination register unmodified, instead of storing zeros in them. Implication: Intel has not observed this erratum with any commercially available software. Workaround: None identified. For the steppings affected, see the Summary Tables of Changes.
  • Page 52 Basic Architecture, for information on the usage of the ENTER instructions. This erratum is not expected to occur in ring 3. Faults are usually processed in ring 0 and stack switch occurs when transferring to ring 0. Intel has not observed this erratum on any commercially available software.
  • Page 53 A or D bits being set in a Page Table Entry (PTE)) Implication: Stale translations may remain valid in TLB after a PTE update resulting in unpredictable system behavior. Intel has not observed this erratum with any commercially available software.
  • Page 54 (due to redundant prefixes placed before the instruction) may lead, under complex circumstances, to unexpected behavior. Implication: The processor may behave unexpectedly due to invalid instructions. Intel has not observed this erratum with any commercially available software.
  • Page 55 • the EFLAGS register are set Implication: If this erratum occurs the stack size may be incorrect, consequently this may result in unpredictable system behavior. Intel has not observed this erratum with any commercially available software. Workaround: None identified. For the steppings affected, see the Summary Tables of Changes.
  • Page 56 Status: AI98. Store Ordering May be Incorrect between WC and WP Memory Types ® According to Intel 64 and IA-32 Architectures Software Developer’s Manual, Problem: Volume 3A "Methods of Caching Available", WP (Write Protected) stores should drain the WC (Write Combining) buffers in the same way as UC (Uncacheable) memory type stores do.
  • Page 57 After an amount of data greater than or equal to the address size structure has been processed, external events (such as interrupts) will cause the (E)CX registers to be incremented by a value that ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
  • Page 58 Implication: (E)CX may contain an incorrect count which may cause some of the STOS operations to re-execute. Intel has not observed this erratum with any commercially available software. Workaround: Do not use values in (E)CX that when multiplied by the data size give values larger than the address space size (64K for 16-bit address size and 4G for 32-bit address size).
  • Page 59 As an example, an access to a memory mapped I/O device may be incorrectly marked as cacheable, become cached, and never make it to the I/O device. Intel has not observed this erratum with any commercially available software.
  • Page 60 APIC access page to avoid such an overlap. Under normal circumstances for correctly written software, such an overlap is not expected to exist. Intel has not observed this erratum with any commercially available software. Workaround: For a fully comprehensive workaround, the VMM should not allow the logging of branch or PEBS records while guest software is running if the "virtualize...
  • Page 61 Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.
  • Page 62 Problem: multiple level one data cache snoops. Implication: Due to this erratum, a livelock may occur. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for BIOS to contain a workaround for this erratum.
  • Page 63 Under certain conditions, as described in the Software Developers Manual Problem: section "Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors", the processor may perform REP MOVS or REP STOS as write combining stores (referred to as “fast strings”) for optimal performance.
  • Page 64 Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest Interruptibility-State Field ® As specified in Section, “VM Exits Induced by the TPR Shadow”, in the Intel Problem: 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, a VM exit occurs immediately after any VM entry performed with the “use TPR...
  • Page 65 Due to this erratum, in a ® system supporting Intel Virtualization Technology, when a VM Exit occurs due to Virtual APIC-Access (Advanced Programmable Interrupt Controller- Access) the EFLAGS/RFLAGS saved in the VMCS (Virtual-Machine Control Structure) may contain an RF value of 0.
  • Page 66 EIP offset in the code segment, resulting in unexpected instruction execution, unexpected exceptions or system hang. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
  • Page 67 Implication: If a benign exception occurs while attempting to call the double-fault handler, the processor may hang or may handle the benign exception. Intel has not observed this erratum with any commercially available software.
  • Page 68 Workaround: It is possible for the BIOS to contain a workaround for this erratum. For the steppings affected, see the Summary Tables of Changes. Status: § ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...

  • Page 69: Specification Changes

    Core™2 Duo desktop processor documentation. Δ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature.

  • Page 70: Specification Clarifications

    Volume 3A: System Programming Guide will be modified to include the presence of page table structure caches, such as the page directory cache, which Intel processors implement. This information is needed to aid operating systems in managing page table structure invalidations properly.

  • Page 71: Documentation Changes

    64 and IA-32 Architectures Software Developer’s ® Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document Intel 64 and IA-32 Architectures Software Developer’s manual documentation changes. Follow the link below to become familiar with this file.

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X6800 - core 2 extreme 2.9 ghz 4m l2 cache lga775 dual-core processorCore 2 extreme x6800Core 2 duo e6000Core 2 duo e4000

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