Impedance Requirements; Recommended Pci Express Stripline Trace Width/Spacing; Trace Width/Impedance Requirement For Stripline And Microstrip Layers - Intel EP80579 Manual

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PCI Express* Interface—Intel
Follow the specified stackup in Figure TBD to avoid frequency-dependent loss effects
that may occur at PCI Express edge rates. If the dielectric characteristics are different
from those specified in the stackup (TBD), the solution space presented in this section
may not apply. This inaccuracy may happen even if the trace widths are adjusted to
meet the specified impedance targets because the attenuation of high frequency
components is a function of the trace width, thickness, and dielectric characteristics.
Simulate and validate any design that deviates from the specified stackup.
10.1.2

Impedance Requirements

The tables in this section show the required geometry for the stripline and microstrip
PCI Express differential signals.
Stripline traces are routed on inner layers. Signals travel slower on stripline traces than
on microstrip traces. They have a very low FEXT and very low dispersion.
indicates the differential impedance and trace width used in routing stripline signals.
Microstrip traces are routed on the outer layers. Signals travel a bit faster on the
microstrip traces compared to stripline traces. They have significant FEXT and notable
frequency and mode dependence on velocity.
impedance and trace width used in routing microstrip signals.
Table 48.

Trace Width/Impedance Requirement for Stripline and Microstrip Layers

Trace Width
4.5 mils
4.75 mils
Figure 87.

Recommended PCI Express Stripline Trace Width/Spacing

Non-
Interface
Signal
18 or 3x dielectric
thickness
Distances in Mils
®
Intel
EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
Nominal Trace Spacing
Stripline Layers (3 or 8)
5.5 mils edge-to-edge
Microstrip Layers (1 or 10)
5.25 mils edge-to-edge
Differential
Pair
4.5
4.5
18 or 3x
5.5
dielectric
thickness
Table 48
indicates the differential
Nominal Trace Impedance
(Zo)
90 Ω ±10% (Differential)
90 Ω ±10% (Differential)
Differential
Pair
4.5
4.5
5.5
18 or 3x dielectric
thickness
Table 48
Non-
Interface
Signal
May 2010
138

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