Clock Signal -- Usb Clk48; Usb Over Current Protection - Oc[1:0]; Plane Splits, Voids, And Cut-Outs (Anti-Etch); Vcc Plane Splits, Voids, And Cut-Outs (Anti-Etch) - Intel EP80579 Manual

Table 64.

USB_RBIASp/USB_RBIASn Routing Summary

Trace
Impedance
50 Ω ±15%
12.2.4

Clock signal -- USB CLK48

The USB Clock 48 MHz is discussed in
12.2.5 USB Over Current protection – OC[1:0]#
Each USB port has an input to indicate when there is an over current condition. These
inputs can be connected to the over current signal of a current limited power
distribution switch. When an over current condition occurs, the switch will drive these
signals low to indicate the condition to the USB controller. If these signals are not used,
pull them up to VCCPSUS with an 10 kΩ resistor.
12.3

Plane Splits, Voids, and Cut-Outs (Anti-Etch)

The guidelines in the following sections apply to the use of plane splits, voids, and cut-
outs.
12.3.1

Vcc Plane Splits, Voids, and Cut-Outs (Anti-Etch)

Use the following guidelines for the Vcc plane:
• Traces must not cross anti-etch since it greatly increases the return path for those
signal traces. This applies to USB 2.0 signals, high-speed clocks, and signal traces
as well as slower signal traces that might be coupling to them. USB signaling is not
purely differential in all speeds (i.e., the Full-Speed Single Ended Zero is common
mode).
• Avoid routing USB 2.0 signals within 25 mils of any anti-etch to avoid coupling to
the next split or radiating from the edge of the PCB.
When breaking signals out from packages, it is sometimes very difficult to avoid
crossing plane splits or changing signal layers, particularly in environments that use
several different voltage planes. Changing signal layers is preferable to crossing plane
splits if a choice has to be made between one or the other.
If crossing a plane split is completely unavoidable, proper placement of stitching caps
can minimize the adverse effects on EMI and signal quality performance caused by
crossing the split. Stitching capacitors are small-valued capacitors, 1 µF or lower in
value, that bridge voltage plane splits close to where high-speed signals or clocks cross
the plane split. The capacitor ends must tie to each plane separated by the split. They
are also used to bridge or bypass power and ground planes close to where a high-speed
signal changes layers. As an example of bridging plane splits, a plane split that
separates V5REF and VCC33 planes must have a stitching cap placed near any high-
speed signal crossing. One side of the cap must tie to V5REF, and the other side must
tie to VCC33. Stitching caps provide a high frequency current return path across plane
splits. They minimize the impedance discontinuity and current loop area that crossing a
plane split creates.
®
Intel EP80579 Integrated Processor Product Line
Platform Design Guide
170
®
Intel EP80579 Integrated Processor Product Line—Universal Serial Bus (USB) Interface
USB_RBIASp/USB_RBIASn
Routing Requirements
Short USB_RBIASp and
USB_RBIASn pins at the
package.
Maximum Trace Signal Length
Length
A = 0.50 inch
(EP80579 to Resistor)
Section 8.2.5, "CLK48 Group" on page
Signal
Matching Referencing
N/A N/A
102.
May 2010
Order Number: 320068-005US