Traces Routed Parallel To Plane - Intel EP80579 Manual

• Stitching vias must not include the thermal relief.
• One stitching via between a pair of traces is good. Two stitching vias, one on either
side of the signal-via pair, is better.
• The minimum distance of a stitching via anti-pad to the signal trace edge is 5 mils.
Figure 11. Tied Together for the Same Potential Planes
Figure 12. Series Capacitor for Different Potential Planes
Figure 13. Stitching Vias Aligned with Signal Vias
Figure 14. Stitching for Layer Changes
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
44
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Intel EP80579 Integrated Processor Product Line—High-Speed Design Concerns
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May 2010
Order Number: 320068-005US