Ac Coupling Requirements; Via Requirements; Recommended Pci Express Microstrip Trace Width/Spacing - Intel EP80579 Manual

Figure 88.

Recommended PCI Express Microstrip Trace Width/Spacing

Non-
Interface
Signal
20 or 3x dielectric
thickness
Distances in Mils
10.1.3

AC Coupling Requirements

Each PCI Express lane is AC coupled between the transmitter and receiver. The AC
coupling capacitor is located on the board for baseboard devices.
AC coupling capacitors of 75–200 nF (0.1 µF recommended) must be placed at the
same location on the traces within the pair. Size 0603 or smaller capacitors are
recommended. C-packs are not allowed for AC coupling capacitors. Also, the same
package size of the capacitor must be used for each signal in a differential pair. Pad
sizes for each capacitor must be minimized.
10.1.4

Via Requirements

All via geometries are preferred 10 mils finished hole, 21 mils pad or 31 mils antipad.
Alternate via geometries will require simulation of the proposed PCI Express
implementation, including electrical models of the via geometry being used.
Via requirements for design consideration appear below:
• Layout recommended that no more than six vias per Tx pair and four vias per Rx
pair should be used on each net in a differential pair on the motherboard when
routing to a PCI Express connector. For PCI Express graphics down solutions, it is
recommended that no more than four(4) vias per Tx pair and four(4) vias per Rx
trace be used. The only time to use the six (6) vias in a topology is when the LAI is
present. Otherwise the max number of vias is four (4).
• Each via is expected to contribute 0.25 to 0.5 dB to the loss budget. The number of
vias on the differential pair must be the same and in the same relative location on
the differential pair to maintain trace symmetry. Avoid placing pads on the inner
layers.
• The number of vias for each signal line within a differential pair - whether or not
that pair is tightly coupled - must be matched because each signal within the diff
pair must stay on the same layers (3 & 8).
®
Intel EP80579 Integrated Processor Product Line
Platform Design Guide
139
®
Intel EP80579 Integrated Processor Product Line—PCI Express* Interface
Differential
Pair
4.75 4.75
5.25 20 or 3x
dielectric
thickness
Differential
Pair
4.75 4.75
5.25
20 or 3x dielectric
thickness
Order Number: 320068-005US
Non-
Interface
Signal
May 2010