Intel EP80579 Manual page 107

8.3.4.2 VDDA Plane Filtering
The VDDA decoupling requirements for a CK410B compliant clock synthesizer are as
follows:
• One 300 Ω (100 MHz) Ferrite Bead is recommended for the VDDA plane.
• 10 µF of bulk decoupling cap in a 1210 package placed close to the VDDA
generation circuitry is recommended for the VDDA plane. Two 4.7 µF caps can also
be used in place of the 10 µF cap.
• One 0.1 µF high-frequency decoupling cap in the 0603 packages should be placed
as close to each VDDA pin as possible.
8.3.4.3 VDD_48 Plane Filtering
The VDD_48 decoupling requirements for a CK410B compliant clock synthesizer are as
follows:
• One 10 Ω series resistor is recommended for the VDD_48 plane.
• One 10 µF of bulk decoupling cap in a 1210 package placed close to the VDD_48
generation circuitry is recommended for the VDD_48 plane.
• One 0.1 µF high-frequency decoupling cap in the 0603 packages should be placed
as close to each VDD_48 pin as possible.
8.3.4.4 Layer 1 Ground Flood
The following drawings show examples of how to create a ground flood underneath the
CK410 and connect the decoupling caps in such as way as to minimize noise coupling
onto the Layer 1 ground flood.
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
107
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Intel EP80579 Integrated Processor Product Line—Platform System Clock
May 2010
Order Number: 320068-005US