Intel EP80579 Manual page 256

Table 92. Sideband Signals (Sheet 3 of 4)
Signal Name
RCIN#
A20GATE
CPURST#
CPUPWRGD_OUT
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
256
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Intel EP80579 Integrated Processor Product Line—Sideband Signals
Group
Keyboard Controller Reset Processor:
• The keyboard controller can generate INIT# to the
• EP80579 ignores RCIN# assertion during
CPU Sideband Input
• Connect to Keyboard Reset (KBDRST#) pin of the
Note:
• This signal should be pulled-up to VCC3 (3.3V)
A20 Gate:
• A signal from the keyboard controller. Acts as an
• Connect to A20M pin of the Keyboard Controller
CPU Sideband Input
• Pull up signal to Platform 3.3V (VCC3) power supply
Note:
• This signal should be pulled-up to VCC3 (3.3V)
Processor Bus Reset:
• The IMCH assets CPURST# while RSTIN# is
• Processor reset output signal that can be used by a
CPU Sideband Output
• Pull up signal to Platform 3.3V (VCC3) power supply
Note:
• This signal can be left as a no connect (NC) if not
CPU Power Good:
• This EP80579 output signal is made visible to the
CPU Sideband Output
• Pull up signal to Platform 3.3V (VCC3) power supply
Description
CPU. This saves the external OR gate of other
sources of INIT#. When EP80579 detects the
assertion of this signal, INIT# is generated for 16
PCICLK clocks.
transitions to the S3, S4 and S5 states.
Keyboard Controller provided by the Super I/O
device.
using a 10KΩ ± 5% resistor .
alternative method to force the A20M# signal
active. Saves the external OR gate needed with
various other chipsets.
provided by the Super I/O device.
using 10KΩ ± 5% resistor
using a 10KΩ ± 5% resistor if not used
asserted and for approximately 1 ms after RSTIN#
is deasserted. The CPURST# allows the processor
to begin execution in a known state.
debug tool.
using 10KΩ ± 5% resistor if used.
used
platform for debug purposes only. This signal is an
open drain signal, and requires an external pull-up
resistor. CPUPWRGD monitors an internal signal
connected directly form the IICH to the processor
and represents a logical AND of PWROK and
VRMPWRGD signals
using 10KΩ ± 5% resistor
Order Number: 320068-005US
May 2010