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Universal Serial Bus (USB) Interface—Intel
• Keep USB 2.0 signals clear of the core logic set. High current transients are
produced during internal state transitions and can be very difficult to filter out.
• Follow the 20*h general guideline by keeping traces at least 20*(height above the
plane) away from the edge of the plane (Vcc or GND, depending on the plane the
trace is over).
For an example, the stackup height above the plane is 4.5 mils. This calculates to a
spacing requirement of 90 mils from the edge of the plane. This helps prevent the
coupling of the signal onto adjacent wires and also helps prevent free radiation of
the signal from the edge of the PCB.
12.2.2
USB Differential Signals – USBp[1:0], USBn[1:0]
The USB interface has two differential pairs for a total of four signals. Route each pair
differentially as microstrip or stripline.
USBp and USBn routing guidelines for three cases:
• Case 1:
on the board. See
• Case 2:
uses a cable to a daughter card panel for the USB connector. The choke is on the
main board rather than on the daughter card panel. See
• Case 3:
uses a cable to a daughter card panel for the USB connector. In this case, the choke
is on the daughter card panel. See
The front panel design option, Case 2, is made on the board using a 0 Ω resistor.
Putting this resistor on the board required a layer change for the USB signals, which
required simulation. The rear panel design option is similar to Case 1 in that it goes
directly to a connector on the board. The front panel option is more stringent since the
header will be connected to a front panel daughter card through a cable. See
12.7, "Front Panel Solutions" on page 173
solutions.
Table 60.
Case 1, USB Routing Guidelines – EP80579 to Connector (Sheet 1 of 2)
Signal Group
Reference Plane
Layer Assignment
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing
Nominal Trace Length
®
Intel
EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
Table 60
gives the routing guidelines for the USB controller to a connector
Figure
109.
Table 61
gives the routing guidelines to implement a front panel option that
Table 62
gives the routing guidelines to implement a front panel option that
Parameter
USBp[1:0], USBn[1:0]
Ground Referenced, Stripline or Microstrip
Layers 1 or 10 (microstrip)
Layers 3 or 8 (stripline)
1
Trace Spacing, edge-to-edge:
Pair-to-pair spacing, edge to edge: 45 mils
minimum
Spacing to clock signals: 45 mils minimum
Spacing to non-clock signals: 45 mils minimum
Keep all lengths as short as possible. Length L2
must be as short as possible to keep the choke as
close to the connector as possible.
LT = 2–11 in. – microstrip (differential)
Table
60,
Table
61, and
Figure
111.
for more information about front panel
Routing Guidelines
90 Ω ±10% (differential)
4.75 mils – microstrip
4.5 mils – stripline
5.25 mils– microstrip
5.5 mils– stripline
2–10 in. – stripline (differential)
Table 62
summarize the
Figure
110.
Section
Figure
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Figure 112
Figure 113
Figure 112
Figure 113
Figure 109
May 2010
165
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