Ep80579-To-Dimm Interconnect Ddr2 Clock Signals - Intel EP80579 Manual

System Memory Interface (DIMM)—Intel
Figure 79.

EP80579-to-DIMM Interconnect DDR2 Clock Signals

EP80579
CLK0/CLK0#
CLK1/CLK1#
CLK2/CLK2#
CLK3/CLK3#
CLK4/CLK4#
CLK5/CLK5#
The differential clock pairs must be routed differentially from the EP80579 pin to their
associated DIMM pins and must maintain the correct isolation spacing from other
signals. Additionally, it is important to maintain the correct spacing and length
matching between the pair to protect the differential integrity.
Figure 80
for the DDR2 differential clocks. Route differential pair signals on the same layer.
The clocks are routed point-to-point. No external terminations are required for the
clock signals because they are terminated on the DIMMs.
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
EP80579
Pad
EP80579 Pin
Package
Trace
A
L
PKG
and Table 41 depict the recommended topology and layout routing guidelines
Board
Breakout
Routing
Routing
C
B
L L
BREAK ROUTE
DIMM 1
DIMM 0
May 2010
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