Intel EP80579 Manual page 297

Table 100. Schematic Checklist (Sheet 14 of 26)
Checklist Items
SATALED#
SATA0GP (GPIO[26]) See General Purpose I/O (GPIO) Interface
SATA1GP (GPIO[29]) See General Purpose I/O (GPIO) Interface
USBp[1:0],
USBn[1:0]
OC[1:0]#
USB_RBIASp
USB_RBIASn
CLK48
PLTRST#
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
297
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Intel EP80579 Integrated Processor Product Line—Schematics Checklist
I/O Type
Recommendations
(Default)
• Can monitor using an LED to
indicate SATA activity.
OD O
• Requires an external 10KΩ pull-
up to EP80579 VCC33 (3.3V)
power supply if used
Universal Serial Bus (USB) Interface
• No external resistors are
required.
• Connect USBp/n[0] and USBp/
I/O
n[1] differential signal pins
through Common Mode Chokes
to USB connector for ESD and
EMI suppression.
• Connect to OC[2:1]# outputs
of a USB current limiter power
distribution switch.
I
• Pull up signals to P3V3_AUX
using a 10KΩ ± 5% resistors
• Short signals USB_RBIASp to
USB_RBIASn at package.
I/O
• Connect shorted signal to a 22.6 Ω
±1% pull-down resistor to ground
• Connect to 48 MHz clock
(USB_48) from the CK410
Clock Synthesizer
I
• Connect clock through a 33 Ω
±5% series resistor.
Power Management Interface
• Connect to EP80579 RSTIN#
input.
O
• Connect to all Platform devices
that require reset.
Comments
Serial ATA LED: This is an open-
collector/open-drain output signal
driven during SATA command activity. It
is to be connected to external circuitry
that can provide the current to drive a
platform LED. When active, the LED is
on. When tristated, the LED is off. An
external pull-up resistor is required.
Note:
• If all SATA ports are not used, this
signal can be left as no connect
(NC)
• Common mode chokes with a target
impedance of 80-90 Ω at 100 MHz
generally provide adequate noise
suppression.
• See Section 12.2.2 for more details.
Note:
• Can be left as no connect (NC)
when the port is not used.
• See Section 12.2.5
Note:
• If these signals are not used, pull up
to EP80579 3.3V Standby voltage
(VCCPSUS) with an 10 kΩ resistor.
• See Section 12.2.3
• Bias connection is required even if
the USB ports are not used.
Note:
• Both UART_CLK and USB_CLK
(CLK48) use the same clock output
(USB_48) from the CK410 Clock
Synthesizer.
• Isolate UART_CLK from USB_CLK
(CLK48) through series resistors.
• Connect CLK48 to a 48 MHz clock
source even if the USB ports are not
used.
• See Section 2.3
• See Section 8.2.5, "CLK48 Group"
on page 102.
Platform Reset: IICH asserts PLTRST#
to reset Platform devices.
Order Number: 320068-005US
May 2010