Powergood Interface; Reset Interface - Intel EP80579 Manual

Intel
7.2.1

Powergood Interface

The EP80579 receives two external powergood signals. The first is IA-32 core
VRMPWRGD and the other is SYS_PWR_OK. SYS_PWR_OK is asserted after at least 102
ms delay from the time that VRMPWRGD goes active and indicates that power has been
stable for at least 99 ms. See
SYS_PWR_OK interfaces.
7.2.2

Reset Interface

The EP80579 receives two reset signals externally.
The first one is the System Reset signal (SYS_RESET#) which can be connected to a
reset button. Designers can connect the System Reset signal (SYS_RESET#) on the
EP80579 directly to a reset button on the system's front panel provided that the front
panel signal is pulled up to 3.3 V standby through a weak pull-up (10 kΩ) resistor. The
EP80579 will debounce signals on this pin (16 ms) and allow the SMBus to go idle
before resetting the system, helping to prevent a slave device on the SMBus from
"hanging" by resetting in the middle of a cycle. See
The second is Resume Reset which is used for resetting the IICH resume well after
power is restored from a power failure. See
7.2.2.1 PWRBTN#
The Power Button signal (PWRBTN#) on the EP80579 can be connected directly to the
power button on the system's front panel. This signal is internally pulled-up in the
EP80579 to Suspend_3.3V (VCCPSUS) through a weak pull-up resistor (15–35 kΩ).
EP80579 has a 16 ms internal debounce logic on this pin. See
7.2.2.2 PLTRST# / PCIRST# Usage Model
The EP80579 asserts the platform reset signal (PLTRST#) during power-up and when a
hard reset sequence is initiated. This signal must be connected to all devices on the
motherboard that require a reset. PLTRST# must also be connected to EP80579's
RSTIN# signal. PCIRST# is the secondary PCI Bus reset signal and must only be
connected to PCI slots or PCI down devices. See
7.2.2.3 IICH Reset
IICH plays the central role in reset and powergood distribution to the whole chip. IICH
receives two powergood signals from platform VRMPWRGD and SYS_PWR_OK.
Assertion of these signals start the reset sequence for EP80579.
IICH generates the central reset signal (known as PLTRST#) that initiates the reset of
IMCH and the rest of the chip. IICH also generates PCIRST# signal for resetting the PCI
device.
7.2.2.4 GbE MAC Reset
There are three GbE MAC devices. Each GbE MAC receives it's reset from internal reset
unit and also requires a hardware external reset signal via the EP80579 SYS_PWR_OK
input. For "normal" operation, the GBE_AUX_PWR_GOOD pin should also be connected
to the SYS_PWR_OK signal. However, since the GbEs also supports Wake-On-LAN and
S3-cold, they may actually be connected to a separate auxiliary power supply. To
support S3-cold, the GBE_AUX_PWR_GOOD pin should be connected to the platform
supplied power good signal from the auxiliary power supply. (see
®
Intel EP80579 Integrated Processor Product Line
Platform Design Guide
86
®
EP80579 Integrated Processor Product Line—Power Management and Reset Interface
Figure 49 for the block diagram showing VRMPWRGD and
Figure 49.
Figure 49.
Figure
Figure 49.
Order Number: 320068-005US
49.
Figure 49)
May 2010