Address, Data, And Control Signals Mezzanine Star Topology Diagram; Address, Data And Control Star Topology Routing Guidelines - Intel EP80579 Manual

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Figure 150. Address, Data, and Control Signals Mezzanine Star Topology Diagram
BUFFER
Via Break out
ADDR
DATA
CNTL
L
ADDR_Brk_out
L L
ADC_Total = ADC_Brk_out +
NOTE: Breakout\ Breakin descriptions are as follows:
1. Routing where trace is 4 mil wide and 4mil spacing is implemented to escape\ enter BGA
2. The Breakout \ Breakin Length is defined from the pin of the BGA, to where 4 mil spacing
increases to the required spacing per SI recommendations.
a). CS = 10 mil edge-to-edge (e2e) for Stripline
b). CS = 12 mil edge-to-edge (e2e) for Microstrip
Table 91. Address, Data and Control Star Topology Routing Guidelines (Sheet 1 of 2)
Routing Layer
Reference Plane
Board Trace Impedance
Trace Width
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
245
®
Intel EP80579 Integrated Processor Product Line—Local Expansion Bus (LEB) Interface
Address, Data and Control Star Topology
(Buffer
MEZZ #1
TL1
L L
ADDR_TL1_route ADDR_TL2_route
L
ADC_TL1_route + 2
Parameter
Mezzanine)
MEZZ #3 MEZZ #2
TL2
TL2
L
ADDR_TL2_route
L L
ADC_TL2_route + ADC_TL3_route +
X
Routing Constraints
Stripline
Ground Referenced
50 Ω
4.5mils (L3/L8)
L
ADC_Brk_in
Microstrip
50 Ω
5.5mils (L1/L10)
May 2010
Order Number: 320068-005US