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®
Sideband Signals—Intel
EP80579 Integrated Processor Product Line
Table 92.
Sideband Signals (Sheet 4 of 4)
Signal Name
IERR#
25.1
CPUSLP_OUT#, INIT33V_OUT#, NMI, SMI_OUT#,
STPCLK_OUT, RCIN#, A20GATE, IERR#
These signals are asynchronous and adhere to the routing recommendations and
topology recommended in
Table 93.
Routing Recommendations for Sideband Signals
Signal Name
CPUSLP_OUT#
INIT33V_OUT#,
NMI,
SMI_OUT#,
STPCLK_OUT,
RCIN#,
A20GATE,
CPURST#,
CPUPWRGD_OUT,
IERR#
Routing Guidelines
• The Sideband Signals are asynchronous signals and may be routed on either
the stripline or microstrip layers
• These signals may change layers, but this should be minimized as much as
possible
Notes:
1.
W represents width of signal;
2.
S represents spacing to any other signal.
®
Intel
EP80579 Integrated Processor Product Line
Order Number: 320068-005US
Group
CPU Sideband Output
Table
93.
Width (W) /
Impedance
Spacing (S)
50Ω
Stripline:
W = 4.5 mils
S = 15.0 mils
Microstrip:
W = 6.0 mils
S = 15.0 mils
Description
EP80579 Internal Error:
• Asserted by the CPU as the result of an internal
error. Assertion of IERR# is usually accompanied by
a SHUTDOWN transaction on the FSB. This
transaction may optionally be converted to an
external error signal (for example, NMI) by
EP80579. The CPU keeps IERR# asserted until the
assertion of INIT33V_OUT# or EP80579 is reset
using SYS_RESET#.
• Connect to GPIO[40] to be used as IOAPIC IRQ35
• Pull up signal to Platform 3.3V (VCC3) power supply
using 10KΩ ± 5% resistor if used.
Note:
• This signal can be left as a no connect (NC) if not
used
Layer
Notes
Stripline
or
Microstrip
1, 2
May 2010
257
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