Ddr2 Control Signal Group Routing Guidelines; Address And Command Signals - Intel EP80579 Manual

System Memory Interface (SODIMM)—Intel
Table A-10. DDR2 Control Signal Group Routing Guidelines
Signal Group
Topology
Reference Plane
Layer Assignment
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing (e2e)
Clearance from other signals
Board Routing Guidelines
Total Trace Length (TTL) = (L
L
BREAKOUT
L
PKG
L
BREAKOUT
L
ROUTE
L
BREAKIN
L
TERM
On-Board Termination
Parallel Termination Resistor (Rtt)
Length/Skew Matching Rules
Length Tuning Requirements
A.4.5.4 Address and Command Signals – DDR_MA[14:0],
DDR_BA[2:0], DDR_RAS#, DDR_CAS#, DDR_WE#
The address/command signals shown in
Table A-11. Address and Command Signals
System Memory Address Signals
Bank Addresses
Row Address Select
Column Address Select
Write Enable
The address/command signals are source-clocked signals that include 15 system
memory address signals (MA[14:0]), 3 bank addresses (BA[2:0]), row address select
(RAS#), column address select (CAS#), and write enable (WE#). The address/
command signals are "clocked" into the SODIMM using the positive edge of the
differential clock signals. The EP80579 drives the address/command and clock signals
together.
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
Parameter
Control Signals (CS#/ODT/CKE)
Point-to-Point
Ground Referenced
Layers 3/8
40 Ω ±10%
6.5 mils
3X Trace Width
20 mils (min)
+
PKG
+ L + L )
ROUTE BREAKIN
See the Intel
for package length information.
Max = 0.8 in
Max = 6.5 in
Max = 0.8 in
Max = 500 mils
75 Ω ±1%
Signal Description
Routing Guidelines for SODIMM
• TTL (CTRL) = 1.0 in - 7.5 in
• TTL (CTRL) = TTL (CMD/ADD) + 3 in
®
EP80579 Integrated Processor Product Line Datasheet
• Trace length skews for the control signals to the termination
resistors (L ) should not exceed 200 mils.
TERM
• The control signals need to match in length within
± 20 mils of each other.
Table A-11 are source-clocked signals.
Signal Name
DDR_MA[14:0]
DDR_BA[2:0]
DDR_RAS#
DDR_CAS#
DDR_WE#
Figure
Figure A-4
Figure A-4
Figure A-4
Figure A-4
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