Gbe Rgmii Receive Path Clock Topology - Intel EP80579 Manual

Figure 140. GbE RGMII Receive Path Clock Topology
L
Pull_up
Pull Up
TL (μs)
EP80579
Via
Receiver
Clock
LCLK_Total_rx =
NOTE: Breakout\ Breakin descriptions are as follows:
1. Routing where trace is 3.75 mil wide and 4mil spacing is implemented to escape\ enter BGA
2. The Breakout \ Breakin Length is defined from the pin of the BGA, to where 4 mil spacing
increases to the required spacing per SI recommendations.
a). Clock = 20 mil edge-to-edge (e2e) for Stripline
b). Clock = 25 mil edge-to-edge (e2e) for Microstrip
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
223
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Intel EP80579 Integrated Processor Product Line—Gigabit Ethernet (GbE) Interface
RGMII Receive Path Clock Topology
(EP80579
V2P5
Rpull up
Break in
LCLK_Brk_in_rx LCLK_Brd_route_rxLCLK_Brk_out_rx
LCLK_Brk_out_rx + LCLK_Brd_route_rx + LCLK_Brk_in_rx
PHY)
Board Break out
PHY
Via
Transmitter
Clock
May 2010
Order Number: 320068-005US