Intel EP80579 Manual page 8

19.0 Gigabit Ethernet (GbE) Interface ................................................................................................. 209
19.1 GbE MAC/LAN Interface Interconnect.............................................................................. 209
19.2 GbE MAC Interface Guidelines......................................................................................... 210
19.3 Frequency Requirements ................................................................................................. 210
19.4 Gigabit Ethernet Interface Signals .................................................................................... 210
19.5 GbE Interface - LAN Connect Interface Guidelines .......................................................... 215
19.5.1 GbE Ethernet Interface - RGMII Mode .............................................................. 215
19.5.2 GbE Ethernet Interface - RMII Mode................................................................. 216
19.6 GbE Transmit and Receive Topology............................................................................... 218
19.6.1 GbE Transmit Topology....................................................................................... 218
19.6.2 GbE Receive Topology........................................................................................ 222
19.7 GbE Serial EEPROM........................................................................................................ 226
19.8 Wake on LAN.................................................................................................................... 226
19.9 GbE RComp ..................................................................................................................... 226
19.10 Crosstalk Considerations.................................................................................................. 227
19.11 Pull-up Termination........................................................................................................... 227
19.12 General Gigabit Ethernet Design Guidelines.................................................................... 227
20.0 IEEE 1588-2008 Hardware Assist Interface ................................................................................ 229
20.1 Input/Output Signal Application ........................................................................................ 230
20.1.1 Input..................................................................................................................... 233
20.1.2 Outputs ................................................................................................................ 233
20.1.3 Board Design Tips ............................................................................................... 233
21.0 Controller Area Network (CAN) Interface .................................................................................... 234
21.1 Input/Output Signal Application ........................................................................................ 235
21.2 Multipoint Topology........................................................................................................... 236
21.2.1 Board Design Tips ............................................................................................... 236
22.0 Local Expansion Bus (LEB) Interface.......................................................................................... 237
22.1 LEB Chip Select Assignment............................................................................................ 237
22.2 LEB Memory Size (LEB_SIZE) Strapping ........................................................................ 238
22.3 LEB Interface Topologies ................................................................................................. 238
22.3.1 LEB Interface Topology at 33 MHz...................................................................... 238
22.3.2 Chip Select Topologies........................................................................................ 239
22.3.3 Address Star Topologies ..................................................................................... 241
22.3.4 Data and Control Star Topology .......................................................................... 242
22.3.5 Mezzanine Card Interconnect.............................................................................. 244
22.3.6 Input/Output Signal Application ........................................................................... 246
22.3.7 Design Notes ....................................................................................................... 247
23.0 Time Division Multiplex (TDM) Interface...................................................................................... 248
23.1 Development Board TDM Support.................................................................................... 248
23.2 SLIC/CODEC Interface..................................................................................................... 248
23.3 Device Connection............................................................................................................ 248
23.3.1 Input/Output Signal Application ........................................................................... 250
23.3.2 Design Notes ....................................................................................................... 250
24.0 Synchronous Serial Port (SSP) Interface .................................................................................... 251
24.1 Development Board SSP Support .................................................................................... 251
24.2 EP80579 SSP Interface.................................................................................................... 251
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Intel EP80579 Integrated Processor Product Line
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Intel EP80579 Integrated Processor Product Line-Contents
May 2010
Order Number: 320068-005US