Page 1 ® Intel EP80579 Integrated Processor Product Line Platform Design Guide May 2010 Order Number: 320068-005US...
Page 2 Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Intel, Intel logo, Intel Core and Pentium, are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
Page 3: Table Of Contents
® Contents—Intel EP80579 Integrated Processor Product Line Contents Introduction............................20 Reference Documentation ....................20 Acronyms and Terminology ....................21 System Overview...........................24 System Architecture Description..................24 2.1.1 EP80579 Features ....................24 Development Board ......................26 2.2.1 Development Board Features ................28 EP80579 External Clock Requirements ................30 Baseboard Requirements ......................32 Development Board Component Placement ..............32...
Page 4 ® Intel EP80579 Integrated Processor Product Line—Contents 5.8.4 Signals Crossing Plane Splits................63 System Power Delivery Guide....................... 64 Terminology and Definitions ....................64 Power Supply........................65 Power Planes........................66 Power Requirements ......................67 Power Delivery Guidelines....................69 6.5.1 IA-32 core Power (VCC_CPU) ................69 6.5.2...
Page 5 10.1.2 Impedance Requirements..................138 10.1.3 AC Coupling Requirements .................139 10.1.4 Via Requirements ....................139 10.1.5 Compensation Resistor Signals Guidelines............140 10.1.6 PCI Express Clocks Routing Guidelines..............140 10.1.7 Topology 1 – EP80579 to PCI Express Connector..........140 ® May 2010 Intel EP80579 Integrated Processor Product Line...
Page 6 10.1.8 Topology 2 – EP80579 to PCI Express Connector with Logic Analyzer Connector142 10.1.9 Topology 3 – EP80579 to PCI Express Down Device ......... 145 10.1.10 Topology 4 – EP80579 to PCI Express Down Device with Logic Analyzer Connector ................148 10.2...
Page 7 ® Contents—Intel EP80579 Integrated Processor Product Line 13.1.2 General Design Considerations ................179 13.1.3 High Power/Low Power Mixed Architecture............179 13.1.4 Calculating the Physical Segment Pull-Up Resistor ..........180 13.2 Enabled System Management Features (Optional)............180 13.3 Enabled System Management Vendors (Optional) ............181 13.4 Development Board System Management Implementation ..........182...
Page 8 ® Intel EP80579 Integrated Processor Product Line—Contents 19.0 Gigabit Ethernet (GbE) Interface ....................209 19.1 GbE MAC/LAN Interface Interconnect................209 19.2 GbE MAC Interface Guidelines..................210 19.3 Frequency Requirements ....................210 19.4 Gigabit Ethernet Interface Signals ..................210 19.5 GbE Interface - LAN Connect Interface Guidelines ............215 19.5.1 GbE Ethernet Interface —...
Page 9 ® Contents—Intel EP80579 Integrated Processor Product Line 24.2.1 Serial Peripheral Interface (SPI) ................252 24.2.2 Microwire* Interface .....................253 24.2.3 Board Design Tip ....................253 25.0 Sideband Signals.........................254 25.1 CPUSLP_OUT#, INIT33V_OUT#, NMI, SMI_OUT#, STPCLK_OUT, RCIN#, A20GATE, IERR#257 26.0 Debug Port Design Guide......................258 26.1 Overview...........................258...
Page 10 ® Intel EP80579 Integrated Processor Product Line—Contents Supported Memory Configurations ................... 337 Overview and Design Considerations................338 Figures Development Board Block Diagram ..................26 Development Board Component Placement – Top View ............32 Development Board Component Placement – Bottom View..........33 PCB Recommended 10-Layer Stack-Up................
Page 11 PCI Express Connector Routing (EP80579 Transmit) ............140 PCI Express Connector Routing (EP80579 Receive) ............141 PCI Express Connector with LAI Connector Routing (EP80579 Transmit) ......143 PCI Express Connector With LAI Connector Routing (EP80579 Receive) ......144 PCI Express Down Device Routing (EP80579 Transmit).............145 PCI Express Down Device Routing (EP80579 Receive)............146...
Page 12 ® Intel EP80579 Integrated Processor Product Line—Contents PCI Express Down Device with LAI Connector Routing (EP80579 Transmit) ..... 148 PCI Express Down Device With LAI Connector Routing (EP80579 Receive) ..... 149 SATA Layout and Routing Example..................152 SATA Tx and Rx Signal Routing Topology ................154 SATA PCB Routing ......................
Page 13 100 MHz SRC/SRC# Clock Routing Guidelines for Down Devices(Except PCI-E) ....97 100 MHz SRC/SRC# Clock Routing Guidelines for PCI Express Slot/Component ....98 CLK33 Routing Guidelines to EP80579, FWH, and LPC Down Devices ......100 CLK33 Routing Guidelines for Two Down Devices ..............101 ®...
Page 14 PCI Express Down Device Routing (EP80579 Transmit)............. 146 PCI Express Down Device Routing (EP80579 Receive)............147 PCI Express Down Device with LAI Connector Routing (EP80579 Transmit) ..... 148 PCI Express Down Device with LAI Connector Routing (EP80579 Receive) ...... 149 No Connect Signals for Unused PCI Express Ports.............
Page 15 Supported SODIMM Memory Capacity for 64-bit Mode............317 DDR2 Unbuffered SODIMM and Unbuffered DIMM Pin Comparison Table ......318 DDR2 Signal Groups......................319 Length Matching Formulas between EP80579 and DDR2 SODIMM ........320 Data and Strobe Signal Group Routing Guidelines..............322 Clock Signal Group Routing Guidelines ................324 Write Operation ODT Table....................325...
Page 16 1Gb Addressing........................336 B-23 2Gb Addressing........................336 B-24 DDR2 Signal Groups......................336 B-25 Memory Configurations Supported by the EP80579 ............338 B-26 Length Matching Formulas for Memory Down Configuration ..........338 B-27 Clock to Memory Device Mapping..................340 B-28 Clock Signal Group Routing Guidelines ................340 B-29 Data and Strobe Signal Group Routing Guidelines..............
Page 17: Revision History
• Updated Table 100, “Schematic Checklist” - changed Reserved20 pin on page 309 to require a May 2010 Pulled Up to 3.3V to align with EP80579 External Design Specification. ® May 2010 Intel EP80579 Integrated Processor Product Line Order Number: 320068-005US...
Page 18 • SIU_CST2 to SIU_CST2# Section 7.0, “Power Management and Reset Interface” Section 7.4, “Power Sequencing” • Deleted Power Sequencing section. Refer to the Intel® EP80579 Integrated Processor Product Line Datasheet, Document Number 320066 for Power Sequencing Timing Diagrams. Section 8.0, “Platform System Clock”...
Page 19 ® Revision History—Intel EP80579 Integrated Processor Product Line Date Revision Description Section 7.0, “Power Management and Reset Interface” Updates: • Update to Figure 49 to indicate the delay between PWROK and VRMPWRGD to be 102ms instead of 12ms • Update to Figure 54 to connect GBE_AUX_PWR_GOOD to SYS_PWR_OK in systems without Sustain Power.
Page 20: Introduction
Carefully follow the design information, schematics and layout checklists provided in this document. These design guidelines ensure maximum flexibility for board designers and reduce the risk of board related issues. Intel performs substantial validation testing based on the design guidelines that are defined in this document. Platforms that do not...
Page 21: Acronyms And Terminology
Application Note 82540EM Gigabit Ethernet Controller Datasheet and Hardware http://developer.intel.com Design Guide Notes: For the latest revision and documentation number, contact your local Intel field representative. Acronyms and Terminology Table 2. Acronyms and Terminology (Sheet 1 of 3) Acronym Definition...
Page 22 Integrated I/O Controller Hub IMCH Integrated Memory Controller Hub 1. Input/Output ® 2. When used as a qualifier to a transaction type, specifies that transaction targets Intel architecture-specific I/O space (e.g., I/O read). Internet Protocol ITP-XDP In Target Probe - Expanded Debug Port...
Page 23 ® Introduction—Intel EP80579 Integrated Processor Product Line Table 2. Acronyms and Terminology (Sheet 3 of 3) Acronym Definition Operating System Peer-to-Peer Peripheral Component Interconnect Local Bus, a 32- or 64-bit bus with multiplexed address and data lines that is primarily intended for use as an interconnect mechanism within a system between processor/memory and peripheral components or add-in cards.
Page 24: System Overview
The architecture is designed to provide high-processing performance, low- power usage, and reasonable cost targets while maintaining IA implementation and providing the required I/O throughput. The EP80579 can be configured to meet many system application and implementation needs. The EP80579 is manufactured on Intel’s advanced 90 nanometer process technology and fully compatible with IA-32 software.
Page 25: Ep80579 Feature List
EP80579 Feature List Universal Serial Bus (USB) IA-32 core • Two ports supported: ® • The core is based on the Intel Pentium M • One Enhanced Host Controller Interface processor and modified for SOC applications. (EHCI) USB 2.0. • Operating frequencies: 600 MHz, 1066 MHz and •...
Page 26: Development Board
Development Board The Development Board is designed as a validation vehicle to test and verify the correct functionality of the EP80579 silicon. It also serves as an example of a validated implementation of the EP80579 silicon for external customers. The Development Board provides interfaces to the extensive peripheral and I/O capabilities (SATA, GbE, USB, PCI Express, etc.) included in the part.
Page 27 ® System Overview—Intel EP80579 Integrated Processor Product Line Figure 1. Development Board Block Diagram Legend EP80579 Connectors Yellow Components ITP-XDP DDR2 Green 60pin 9 pin D-sub Transceiver Header 9 pin D-sub SMBus Transceiver Header 9 pin D-sub UART RS232 XCVR...
Page 28: Development Board Features
® Intel EP80579 Integrated Processor Product Line—System Overview 2.2.1 Development Board Features Table 4. Development Board Feature List (Sheet 1 of 3) Feature Board Implementation Comments CPU Support IA-32 core EP80579 Processor core IA-32 core Internal bus only no connector...
Page 29 Test headers for PCI Express midbus on all 8 lanes logic analyzer System Management Bus (SMBus) One Primary SMBus from the EP80579 with three Repeaters (SMBus A/B/C) for voltage translation, fanout, and isolation • Primary SMBus SIO, SMLink Connectivity •...
Page 30: Ep80579 External Clock Requirements
Two CAN connectors - 2x5 Headers with pin 10 key 3x slots TDM Mezzanine slots EP80579 External Clock Requirements External clocks are supplied to EP80579 internal PLLs as the reference clocks and to other I/O devices. EP80579 has internal PLLs that use these reference clocks to generate internal clocks.
Page 31 ® System Overview—Intel EP80579 Integrated Processor Product Line Table 5. EP80579 External Clock Requirements Clock Domain Frequency Source Description SATA_CLKREF(p/n) 100 MHz External SATA Reference Clock CLK48 (USB) 48 MHz External USB Clock CLK14 14.31818 MHz External Timer Oscillator Clock...
Page 32: Baseboard Requirements
® Intel EP80579 Integrated Processor Product Line—Baseboard Requirements Baseboard Requirements Development Board Component Placement Table 6 lists the assumptions used for the component placement of the Development Board. See www.formfactors.org for detailed information on the ATX specification. Table 6. Assumptions for System Placement Example...
Page 33: Development Board Component Placement - Bottom View
® Baseboard Requirements—Intel EP80579 Integrated Processor Product Line Figure 2. Development Board Component Placement – Top View CPU SEL PCI-E x4-1 DB800 CK410 PCI-E x4-2 PCI-E x4-3 PCI-E x4-4 PCI-E x8 ® Intel EP80579 Integrated Processor Product Line May 2010...
Page 34: Pcb Recommended 10-Layer Stack-Up
® Intel EP80579 Integrated Processor Product Line—Baseboard Requirements Figure 3. Development Board Component Placement – Bottom View ® Intel EP80579 Integrated Processor Product Line Platform Design Guide May 2010 Order Number: 320068-005US...
Page 35: Platform Stack-Up
Signal layers are dual referenced asymmetric stripline on layers 3, 5, 6, and 8 and microstrip on layers 1 and 10. Signal layers 1, 3, 5, 6, 8, and 10 are referenced to ground. Intel strongly recommends that system designers use the stack-up shown in Figure 4 and recommendations in Table 7 when designing their boards.
Page 36: Mounting
® Intel EP80579 Integrated Processor Product Line—Baseboard Requirements Table 7. Development Board Summary Board Factor Recommendation • Standard FR4 Tg 170 Epoxy Material • 370HR used for lead free • DDR2: • Varies depending on the layer, the signal, and the topology used.
Page 37: Component Quadrant Layout
EP80579 Integrated Processor Product Line—Component Quadrant Layout Component Quadrant Layout Figure 5 Figure 6 show only general quadrant information for the EP80579 component, and not exact component pin placement. Designers must use the exact pin ® assignment to conduct routing analysis. See the Intel EP80579 Integrated Processor Product Line Datasheet for exact ball assignment information.
Page 38: Quadrant Layout
® Component Quadrant Layout—Intel EP80579 Integrated Processor Product Line Quadrant Layout Figure 5. Quadrant Layout (Top View) AN AM AL AK AJ AH AG AF AE AD AC AB AA Y SSP, 1588 JTAG GPIO UART IMCH/ IICH SATA Power/Ground...
Page 39 ® Intel EP80579 Integrated Processor Product Line—Component Quadrant Layout Figure 6. Quadrant Layout (Bottom View) SSP, 1588 JTAG GPIO UART IMCH/ IICH SATA Power/Ground PCIE Bottom View ® Intel EP80579 Integrated Processor Product Line Platform Design Guide May 2010 Order Number: 320068-005US...
Page 40: High-Speed Design Concerns
EP80579 Integrated Processor Product Line—High-Speed Design Concerns High-Speed Design Concerns This chapter describes basic high-speed design practices as they apply to the EP80579. Return Path The return path is the route current takes to return to its source. It may take a path through ground planes, power planes, other signals, or integrated circuits.
Page 41: Bulk Decoupling
® High-Speed Design Concerns—Intel EP80579 Integrated Processor Product Line The inductance of the system caused by cables and power planes slows the power supply's ability to respond quickly to a current transient. Decoupling a power plane may be broken into several independent parts. More inductance is bypassed by placing the capacitors closer to the load.
Page 42: High Speed Differential Routing Rules
Parameter “H” is the distance between the signal and the referenced plane. The ratio is specified as S/H. For the EP80579 stack-up this ratio is typically 3:1. Check the guidelines for each interface to ensure the proper ratio is being used.
Page 43: Serpentine Line Rules For Differential Signals
® High-Speed Design Concerns—Intel EP80579 Integrated Processor Product Line 5.4.1 Serpentine Line Rules for Differential Signals Figure 10. Serpentine Line Minimum Serpentine Length = 100 mils Minimum Serpentine Width = 30 mils A meander or serpentine line is a transmission line routed in such a manner that segments of the line zigzag and couple to the other segments of the same line.
Page 44: Traces Routed Parallel To Plane
® Intel EP80579 Integrated Processor Product Line—High-Speed Design Concerns • Stitching vias must not include the thermal relief. • One stitching via between a pair of traces is good. Two stitching vias, one on either side of the signal-via pair, is better.
Page 45: Trace Segment Length Equalization, Bend, And Spacing
® High-Speed Design Concerns—Intel EP80579 Integrated Processor Product Line 5.4.3 Trace Segment Length Equalization, Bend, and Spacing The following are several general rules regarding the length matching and other factors when routing high speed differential signal (see Figure 16 when reviewing these rules): •...
Page 46: Trace Mismatch And Compensation
® Intel EP80579 Integrated Processor Product Line—High-Speed Design Concerns Figure 16. Trace Segment Length Equalization Length of M aintain the Lateral Symmetry Segments for Traces 5.4.4 Trace Mismatch and Compensation The following rules describe how to handle trace mismatch (see...
Page 47: Routing Examples Of The Length Compensation #2
® High-Speed Design Concerns—Intel EP80579 Integrated Processor Product Line Figure 18. Trace Length Mismatch Corners Figure 19. Routing Examples of the Length Compensation #1 Δl < 10 mils: No length compensation is Length compensation within the pin field. required. ®...
Page 48: Dc Blocking Capacitor
The following sections describe design techniques that may be applied to minimize EMI emissions. Some techniques have been incorporated into Intel-enabled designs (differential clock drivers, selective clock gating, etc.), while others must be implemented by motherboard designers (trace routing, clocking schemes, etc.).
Page 49: Brief Emi Theory
® High-Speed Design Concerns—Intel EP80579 Integrated Processor Product Line 5.5.1 Brief EMI Theory Electromagnetic energy transfer may be viewed in four ways: • Radiated emissions • Radiated susceptibility • Conducted emissions • Conducted susceptibility For system designers, reduction of radiated and conducted emissions is the way to achieve EMC compliance.
Page 50: Spread Spectrum Clocking (Ssc)
® Intel EP80579 Integrated Processor Product Line—High-Speed Design Concerns Processor performance and frequency double approximately every two years. With this in mind, it is advisable to be prepared for the frequencies that may need to be scanned in the next few years.
Page 51: Differential Clocking
® High-Speed Design Concerns—Intel EP80579 Integrated Processor Product Line Figure 23. Impact of Spread Spectrum Clocking on Radiated Emissions Δ non-SSC (1-δ)f 5.5.5 Differential Clocking Differential clocking requires the clock generator supply both clock and clock-bar traces. Clock-bar has equal and opposite current as the primary clock and is also 180°...
Page 52: Length Tuning
® Intel EP80579 Integrated Processor Product Line—High-Speed Design Concerns Differential clocking may also reduce the amount of noise coupled to other traces, which improves signal quality and reduces EMI. I/O signals are particularly important, because they often leave the system chassis (serial and parallel ports, keyboards, mouse, etc.) and radiate noise that has been induced onto them.
Page 53: Signal-To-Strobe Flight Time Relationships
® High-Speed Design Concerns—Intel EP80579 Integrated Processor Product Line 5.6.1 Signal-to-Strobe Flight Time Relationships High-speed interfaces are commonly latched off a strobe or a clock. Length tuning ensures that the required setup and hold times of the data signal to the strobe signal or clock signal are not violated due to motherboard routing effects.
Page 54: Flight Time Segment Analysis
® Intel EP80579 Integrated Processor Product Line—High-Speed Design Concerns When the strobes are the furthest apart (that is, as far apart as allowed for signals of the same group), then their difference is the total allowed tolerance. This means that all signals must fall between them, or have a solution space, which is “tolerance”...
Page 55: Package Trace Length Differences
® High-Speed Design Concerns—Intel EP80579 Integrated Processor Product Line compensate for package-induced skew, the signals lengths in the same group are adjusted by the exact amount of Package Length Compensation (PLC). Equation 1defines PLC for a particular signal. Signal X is any signal in the group that does not have the longest package length.
Page 56: Bus Length Tuning Methodology
Using the PCB trace length for this signal, the solution space of remainder signals and strobes in the group can be determined. Intel is able to provide a length tuning calculator spreadsheet. The calculator uses all the specific routing parameters specified in previous section (minimum and maximum lengths, tolerances, signal groups, and so on) to determine the solution space for the bus in question.
Page 57: Common Layout Pit-Falls
® High-Speed Design Concerns—Intel EP80579 Integrated Processor Product Line Each of the signals will have varying amounts of package skew. The amount of skew for a particular signal is based on the difference between that signal’s package trace length and the longest signal’s package trace length in the same signal group. For example, signals with shorter package length will have more package trace length compensation than signals with package lengths closer to the longest package trace.
Page 58: Improper Via Sharing
® Intel EP80579 Integrated Processor Product Line—High-Speed Design Concerns Figure 33. Signal Parallelism Proper adjacent layer signal routing Improper adjacent signal layer routing ® Intel EP80579 Integrated Processor Product Line Platform Design Guide May 2010 Order Number: 320068-005US...
Page 59: Via Sharing
® High-Speed Design Concerns—Intel EP80579 Integrated Processor Product Line 5.8.2 Via Sharing To minimize inductance/impedance, traces must not share vias. Figure 34 shows the improper method of via sharing. Figure 35 shows an proper method of how to connect the vias.
Page 60: Necking Down
® Intel EP80579 Integrated Processor Product Line—High-Speed Design Concerns Figure 35. Correct Via Connections C808 and C726 corrected to have their own vias 5.8.3 Necking Down To maintain the current carrying capacity of a thicker power/ground trace, do not neck the trace down.
Page 61: Correct Necking Down
® High-Speed Design Concerns—Intel EP80579 Integrated Processor Product Line of the thicker traces. Figure 36 shows the improper method of necking down. To correct this issue, the same trace may be routed on several different layers and connected by an adequate amount of vias. A second option is shown in Figure 37.
Page 62: Signal Crossing Plane Splits
® Intel EP80579 Integrated Processor Product Line—High-Speed Design Concerns Figure 37. Correct Necking Down Neck down corrected by adding additional trace. Traces are equal in length and width. ® Intel EP80579 Integrated Processor Product Line Platform Design Guide May 2010...
Page 63: Signals Crossing Plane Splits
® High-Speed Design Concerns—Intel EP80579 Integrated Processor Product Line 5.8.4 Signals Crossing Plane Splits Signals that cross an adjacent layer’s plane boundary are undesirable for two reasons: • The return current that runs in the reference plane wants to share its current with the adjacent layer’s reference plane it just crossed over.
Page 64: System Power Delivery Guide
Intel EP80579 Integrated Processor Product Line—System Power Delivery Guide System Power Delivery Guide This chapter provides an example for board power delivery of an EP80579-based platform design. It provides the requirements and implemention of power sources for system board designs.
Page 65: Power Supply
Table Note: The EP80579 is a large chip and may have interfaces that are not located near each other, although they are powered by the same voltage. These voltages are not necessarily connected in the package or on the silicon. Their source voltage may be the same voltage plane on the baseboard, but they need to be considered separate for decoupling purposes on the board.
Page 66: Power Planes
® Intel EP80579 Integrated Processor Product Line—System Power Delivery Guide Table 9. Power Supply Pins (Sheet 2 of 2) Development EP80579 Well Board Power Pin Supply Types Description Voltage Rail Name VCC1P2_USBSUS USB2 1.2V USB sustain power 1.2V VCCSUS1 IMCH_PAD RTC core sustain power 2.5V...
Page 67: Power Requirements
CRU Analog Voltages VCCAHPLL VCCAHPLL 1.2V Analog Power for CRU PLL Power Requirements This section describes the power requirements for the EP80579. Figure 39 shows a block diagram of the power delivery implementation on the Development Board. Table 11 provides the definitions for the voltages specified in Figure 39.
Page 68 ® Intel EP80579 Integrated Processor Product Line—System Power Delivery Guide Figure 39. Development Board Power Delivery Implementation EP80579 Development Board Power Delivery Block Diagram +12VPC 1.2V 1.0V 2.5V V1P2 V1P0 V2P5 VCC-CPU 5.0V 1.0 – 1.3 V 5.0V 1.0V 2.0V...
Page 69: Power Delivery Guidelines
6.5.1.1 IA-32 core Bus Frequency and Power Select The IA-32 core voltage is controlled by two signals (BSEL & V_SEL) from the EP80579. The BSEL and V_SEL signals are driven by EP80579 to reflect the internal strapping of the various EP80579 SKUs. The BSEL/V_SEL encodings should be interpreted to...
Page 70: Core Logic Voltage (V1P2)
The V1P2 (1.2V) power plane is derived from the 5V power rail delivered by the power supply unit through a switching regulator. It powers the EP80579 core logic and the I/O buffer cells for SATA, PCI Express, and Expansion Bus interfaces.
Page 71: Vcc3)
® System Power Delivery Guide—Intel EP80579 Integrated Processor Product Line 6.5.7 3.3V (VCC3) The VCC3 (3.3V) power plane comes directly from 3.3V power rail delivered by the power supply. This power plane is used for all 3.3V I/O functions that are not dedicated to their own power rail.
Page 72: Auxiliary Voltages
® Intel EP80579 Integrated Processor Product Line—System Power Delivery Guide typically used to derive other stand-by power planes (e.g., 3.3 VSBY, 2.5 VSBY, etc.) on the Development Board. The power supply should be capable of handling at least 2A of continuous standby current and at least 2.5 A of peak standby current.
Page 73: Voltage Regulator Design Recommendations
® System Power Delivery Guide—Intel EP80579 Integrated Processor Product Line due to the transition or switching loss as it switches on and off. To minimize the transition loss in the control MOSFET, its transition time must be minimized. This is usually accomplished with the use of a small-size MOSFET.
Page 74: High Current Path During Abrupt Load Current Changes
® Intel EP80579 Integrated Processor Product Line—System Power Delivery Guide Figure 41. Buck Voltage Regulator Example V_DC NMOS DRIVER Output Vcc NMOS RLoad SCHOTTKY Voltage IMVP-IV Regulator Control Feed back Control Circuitry Circuitry 6.6.3.1 High Current Path, Top MOSFET Turned ON...
Page 75: High Current Path With Bottom Mosfet(S) Turned On
® System Power Delivery Guide—Intel EP80579 Integrated Processor Product Line Figure 43. High Current Path During Abrupt Load Current Changes Voltage Regulator Control Circuitry 6.6.3.3 High Current Paths During Switching Dead Time When the top MOSFET turns OFF and before the bottom MOSFET (there may be more than one of these) is turned ON, the pattern of current flow changes.
Page 76 ® Intel EP80579 Integrated Processor Product Line—System Power Delivery Guide Figure 45. High Current Path With Bottom MOSFET(s) Turned ON Voltage Regulator Control Circuitry 6.6.3.5 General Layout Recommendations All of the components in the high current paths dissipate some power (i.e., they get warm when current runs through them).
Page 77: Power Plane Filter Requirements
® System Power Delivery Guide—Intel EP80579 Integrated Processor Product Line • Use bulk capacitors for the voltage regulator and multiple layer traces with heavy copper to keep the parasitic resistance low. Use a minimum of three vias per connection on each bulk capacitor.
Page 78: Analog/Bandgap Filter Topology
® Intel EP80579 Integrated Processor Product Line—System Power Delivery Guide • Analog Voltage Filter • Bandgap Filter 6.6.4.1 Recommended Filter Topologies for Analog (PLL) and Bandgap Filters Figure 47 shows the recommended filtering for Analog (PLL) and Bandgap supplies, and Table 13 provides the recommended component values for the filters.
Page 79: Analog And Bandgap Filter Layout Guidelines
• These supplies must have a via directly from the supply plane. • The filter must be placed as close as possible to the EP80579. • For filters that call out a distinct VSS, place the 0.1 uF capacitor as close as possible to the filters power and ground pins, even though they are connected to the VSS ground plane.
Page 80: Thermal Power Dissipation
® Intel EP80579 Integrated Processor Product Line—System Power Delivery Guide Figure 48. Filter Frequency Response Specification .2dB x dB orbidden Zone -28dB orbidden Zone -34dB 1.67 GHz 1 Hz 1 MHz 66 MHz peak core < 5 k Hz passband...
Page 81: Decoupling Recommendations
Decoupling Recommendations This section details the decoupling required by the EP80579. 6.7.1 VCCVC (IA-32 core Power) Decoupling Care must be taken to reduce the loop inductance for the whole delivery path.
Page 82: Vccape (1.2V, Pci Express Power) Decoupling
® Intel EP80579 Integrated Processor Product Line—System Power Delivery Guide • One 10 µF,±20% 6.3V X7R capacitors are recommended as bulk decoupling. 6.7.4 VCCAPE (1.2V, PCI Express Power) Decoupling • Three 0.1 µF ±10%, 16V X7R capacitors are recommended. • One 10 µF,±20% 6.3V X7R capacitors are recommended as bulk decoupling.
Page 83: Vcc50 (5.0V Reference) Decoupling
® System Power Delivery Guide—Intel EP80579 Integrated Processor Product Line 6.7.10 VCC50 (5.0V Reference) Decoupling • Five 0.1 µF ±10%, 16V X7R capacitors are recommended. • Two 10 µF ±20% 16V Y5V capacitors are recommended as bulk decoupling. 6.7.11 VCCPRTC (Battery Power) Decoupling •...
Page 84: Power Management And Reset Interface
Reset and Powergood Distribution 7.1.1 Types of Reset The EP80579 has four types of reset: Power-good (cold) reset, hard reset, CPU-only reset, and targeted I/O subsystem reset(s). Each of these reset subclasses have unique effects and is described in Table Table 14.
Page 85: Software Controlled Reset
7.1.5 CPU (IA-32 core) Only Reset For power management, error conditions, and other reasons, the EP80579 supports a targeted CPU only reset semantic. This mechanism eliminates system reset at large when the CPU function (such as clock gearing selection) must be updated during initialization.
Page 86: Powergood Interface
3.3 V standby through a weak pull-up (10 kΩ) resistor. The EP80579 will debounce signals on this pin (16 ms) and allow the SMBus to go idle before resetting the system, helping to prevent a slave device on the SMBus from “hanging”...
Page 87: Reset Sequence
(from platform) to EP80579 7.2.3.1 Reset Procedure 1. EP80579 receives power and drives its BSEL and V_SEL pins. IA-32 core VRMPWRGD, and SYS_PWR_OK are not asserted. PLTRST# (platform signal) and CPURST# (internal signal) are asserted. 2. VRMPWRGD is asserted (platform signal).
Page 88: Power Management
7.3.1 Supported Power States EP80579 can be switched to a very low power state during what looks like to the user as “off”. The traditional PC power states typically supported by IA-32 core, IMCH and IICH components are employed by the EP80579 for this goal.
Page 89: Clock Control States
® Power Management and Reset Interface—Intel EP80579 Integrated Processor Product Line Figure 51. Clock Control States 7.3.1.3.1 Normal State (C0) This is the normal operating state for the IA-32 core. 7.3.1.3.2 AutoHALT Powerdown State (C1) AutoHALT is a low-power state entered when the IA-32 core executes the HALT instruction.
Page 90: Power Sequencing
® Intel EP80579 Integrated Processor Product Line—Power Management and Reset Interface While in the Stop-Grant State, SMI#, INIT# and LINT[1:0] will be latched by the IA-32 core, and only serviced when the IA-32 core returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state.
Page 91: Platform System Clock
® Intel EP80579 Integrated Processor Product Line—Platform System Clock Platform System Clock The Development Board uses a single CK410 clock synthesizer, as well as DB800 x8 companion buffer solutions, to minimize jitter, improve routing, and reduce cost. The CK410 provides three differential CPU host clock pairs and one selectable differential CPU/SRC clock.
Page 92: Ck410 Clock Groups
SRC_IN(p/n) Slot PCI Express PEA_REFCLK(p/n) CLK100 PCI Express x8 Slot PCIE_x8_100_MHz_(p/n) SATA SATA_CLKREF(p/n) EP80579 - ICH 14 MHZ Clock CLK14 CLK14 SIO - LPC 14 MHZ Clock CLOCKI PCI_0 Port80 - PORT80 33 MHz Clock GCLK PCI_1 FWH - FWH 33 MHz Clock...
Page 93: Development Board Clocking Diagram
® Intel EP80579 Integrated Processor Product Line—Platform System Clock Figure 52. Development Board Clocking Diagram Development Board Clocking ITP_BCLK CPU_2/ CPU_2# 100MHz_CORE_Diff CPU_0/ CPU_0# Memory 125MHZ_CLK 25MHZ_CLK 25 MHz GbE PHY ICH_USB_48MHZ_CLK Crystal USB_48 ICH_14MHZ_CLK 8.192 MHz E1 / T1 I/O...
Page 94: System Clock Groups
Topology and Routing guidelines provided in this section applies to the routing of the differential clocks from the clock synthesizer to EP80579 or to the ITP Debug Port The clock driver differential bus output structure is a “current mode current steering”...
Page 95: Trace Spacing For Host_Clk Clocks
® Intel EP80579 Integrated Processor Product Line—Platform System Clock Table 18. HOST_CLK Routing Guidelines Parameter Routing Guidelines Figure Host_CLK: Signal Group • EP80579 (CLKP100/CLKN100) • ITP Debug Port (BCLKP/BCLKN) Reference Plane Ground Referenced, Microstrip or stripline Layer Assignment Layers 3 or 8 Characteristic Trace Impedance (Zo) 100 Ω...
Page 96: Clk100 (Src Clock) Group
® Platform System Clock—Intel EP80579 Integrated Processor Product Line 8.2.2 CLK100 (SRC Clock) Group The differential 100 MHz clock synthesizer (SRC) is the source to the PCI Express, SATA and an input to the DB800 differential buffer. The DB800 buffer provides outputs to the PCI Express I/O components.
Page 97: Source Clock Topology To Down Devices (Except Pci-E)
® Intel EP80579 Integrated Processor Product Line—Platform System Clock 8.2.2.3 Source Clock to Down Devices Figure 55. Source Clock Topology to Down Devices (Except PCI-E) LT = L1 + L2 + L4 C lock D river SATA, or other C K410...
Page 98: Clk100 Clock Group (Src Clock) Topology
® Platform System Clock—Intel EP80579 Integrated Processor Product Line 8.2.2.4 Source Clock to PCI Express* Components or Connectors Figure 56. CLK100 Clock Group (SRC Clock) Topology LT = L1 + L2 + L4 C lock D river C K410, D B800...
Page 99: Clk33 Group
Devices (LPC Devices) Notes: The 33 MHz clock to the EP80579 length, “Z”, can be 2” to 20” long and will dictate the length of all other 33 MHz clock signals. Figure 58 will be referenced in all subsequent 33 MHz clock routing sections.
Page 100: Topology For Clk33 To Down Devices
Figure 59. Topology for CLK33 to Down Devices EP80579 or Down Devices Clock Driver Table 21. CLK33 Routing Guidelines to EP80579, FWH, and LPC Down Devices Parameter Routing Guidelines Illustrations Notes Clock Group CLK33: 33 MHz clocks - Port80, FWH, LPC, TPM, SIO,...
Page 101: Clk14 Group
The value of Rs may need to be increased for shorter trace lengths to minimize overshoot / undershoot effects. Length “Z” is the distance from the 33 MHz clock driver to the EP80579 33 MHz input buffer. “Z” can ”...
Page 102: Clk48 Group
REFCLK Ground Plane 8.2.5 CLK48 Group The driver in the CLK48 group is the clock synthesizer USB clock output buffer, USB_48. The receivers are the CLK48 input buffers on the EP80579. ® Intel EP80579 Integrated Processor Product Line May 2010...
Page 103: Ck410 General Design Guides
® Intel EP80579 Integrated Processor Product Line—Platform System Clock Note: These clocks are asynchronous to any other clock on the board. Figure 64. Topology for CLK48 Group LT=L1+L2 Clock EP80579 Driver Table 24. CLK48 Routing Guidelines Parameter Routing Guidelines Figure...
Page 104: Clock Power Delivery
® Platform System Clock—Intel EP80579 Integrated Processor Product Line • The VSS pins should not be connected directly to the VSS side of the caps. They should be connected to the ground flood under the part which is via’d to the ground plane in order to avoid VDD glitches propagating out, getting coupled through the decoupling caps to the VSS pins.
Page 105: Clock Power Groupings For Decoupling / Filtering
® Intel EP80579 Integrated Processor Product Line—Platform System Clock Figure 66. Clock Power Groupings for Decoupling / Filtering V D D _ P C I P C I_ 2 V S S _ PC I P C I P C I_ 1...
Page 106: Ck410 Power Plane Filtering
® Platform System Clock—Intel EP80579 Integrated Processor Product Line Figure 67. Decoupling and Filtering Per Clock Group Optional Ferrite eads may be used to ease routing 3.3V 3.3V 3.3V 3.3V Ferrite ead Specifications DC resistance 0.1-0.3 ohms IF 1= Impedance@100MHz >=100 ohms...
Page 107 ® Intel EP80579 Integrated Processor Product Line—Platform System Clock 8.3.4.2 VDDA Plane Filtering The VDDA decoupling requirements for a CK410B compliant clock synthesizer are as follows: • One 300 Ω (100 MHz) Ferrite Bead is recommended for the VDDA plane.
Page 108: Ground Flood On Layer 1 Underneath Ck410
® Platform System Clock—Intel EP80579 Integrated Processor Product Line Figure 68. Ground Flood on Layer 1 Underneath CK410 CK410 Vdd PCI Vss PCI Vss PCI Vss REF Vdd PCI Vdd REF Vdd 48 Vss CPU Vss 48 Vss Plane on Layer-1...
Page 109: Edge Decoupling Caps - Examples
® Intel EP80579 Integrated Processor Product Line—Platform System Clock Figure 69. Edge Decoupling Caps – Examples Recommended Vss A Vdd A Not Recommended Vss A Vdd A ® Intel EP80579 Integrated Processor Product Line Platform Design Guide May 2010 Order Number: 320068-005US...
Page 110: Iref
® Platform System Clock—Intel EP80579 Integrated Processor Product Line Figure 70. Decoupling Capacitors Placement and Connectivity Decoupling Caps Decoupling Caps VDD_A VDD_48 8.3.5 IREF The IREF pin on the CK410 is connected to ground through a 475 Ω ±1% resistor, making the IREF 2.32 mA.
Page 111: System Memory Interface (Dimm)
EP80579 Integrated Processor Product Line—System Memory Interface (DIMM) System Memory Interface (DIMM) This chapter contains topologies and routing guidelines for the EP80579 DDR2 system memory interface. It provides the DDR2 implementation solution for system designs requiring two DIMMs, unbuffered or registered, operating at 400/533/667/800 MT/s speed rates.
Page 112: Supported Dram Capacity For 64-Bit Mode
1 Gb 2 Gb Note: In the 32b mode, all unused EP80579 DDR2 Data Bus Interface signals should be pulled high to DDR2 1.8V through 10 Kohm resistors. Table 30 shows the supported DDR2 device speed grades for single and Dual DIMMs.
Page 113: Rules For Populating Dimm Slots
® Intel EP80579 Integrated Processor Product Line—System Memory Interface (DIMM) Table 30. Supported DDR2 Data Speeds 1 DIMM 1 DIMM 2 DIMMs DDR Speed 1 rank 2 ranks 1 rank each R = 1T R = 1T R = 1T...
Page 114: Dram Addressing
® System Memory Interface (DIMM)—Intel EP80579 Integrated Processor Product Line Table 32. Supported DDR2 Rank Configurations in Single and Dual DIMM mode (Sheet 2 of 2) Single DIMM Dual DIMM (64 bits - rank 0 & rank 1) (64 bit only)
Page 115: 1Gb Addressing
® Intel EP80579 Integrated Processor Product Line—System Memory Interface (DIMM) Table 35. 1Gb Addressing DDR2 Configuration 128 Mb x 8 # of Banks Bank Address BA0-BA2 Auto Precharge Row Address A0-A13 Column Address A0-A9 Page Size Table 36. 2Gb Addressing...
Page 116: Ddr2 Dimm Ordering Overview
Figure 71). In addition, dual-rank DIMMs must be populated farthest from the EP80579 since only one dual rank DIMM is supported. This recommendation is based on the chip select and on-die termination signals routing requirements of the DDR2 interface. Intel recommends checking for correct DIMM placement during BIOS initialization.
Page 117: System Memory Design Guidelines
The EP80579 has a single channel memory interface. The channel consists of 64 data and 8 ECC bits. The pinout for the channel has been optimized for a baseboard design with two DDR2 DIMMs. The DIMM closest to EP80579 is DIMM1, and the farthest is DIMM0.
Page 118: Ddr2 Signal Groups
® System Memory Interface (DIMM)—Intel EP80579 Integrated Processor Product Line Table 37. DDR2 Signal Groups (Sheet 1 of 2) Group Signal Name Description Data, Mask, & Strobe DDR_DQ[0..7], Byte 0 DDR_DM0, & Data Byte Lane0 DDR_DQS0/DQS0# DDR_DQ[8..15], Byte 1 DDR_DM1, & DQS1/...
Page 119: Package Length Compensation
Table The Command/Address and Control signals require external terminations. External terminations are not required for DQ and DQS signals since both the EP80579 and the SDRAMs contain internal ODT. The following sections provide the detailed topology and routing guidelines for each of the signal groups.
Page 120: Topologies And Routing Guidelines
® System Memory Interface (DIMM)—Intel EP80579 Integrated Processor Product Line Figure 75. DDR2 Interfaced System Interconnect DDR2_VTT DIMM 1 DIMM 0 Command/Address EP80579 CS0#, CKE0, ODT0 CS1#, CKE1, ODT1 CLK0, CLK0# DDR2 CLK1, CLK1# CLK2, CLK2# Memory CLK3, CLK3# Controller...
Page 121: Data/Mask/Strobe Signal Routing Topology Diagram
® Intel EP80579 Integrated Processor Product Line—System Memory Interface (DIMM) Figure 77. Data/Mask/Strobe Signal Routing Topology Diagram EP80579 DIMM 1 DIMM 0 EP80579 EP80579 EP80579 Package Dimm2Dimm Breakout Board Trace Routing Routing Routing BREAK ROUTE Table 39. Data and Strobe Signal Group Routing Guidelines (Sheet 1 of 2)
Page 122: Data And Strobe Signal Group Routing Guidelines
Figure 77 BREAK ROUTE 400 mils ® See the Intel EP80579 Integrated Processor Product Line Datasheet for package length information. B = 0.8 in (max) BREAK Calculate while taking into C = 2.0 in - 4.0 in account Strobe Max Trace...
Page 123: Example Length Matching For A Data Byte Lane
9.7.1.2 DDR2 Clock Group Signals - DDR_CLK[5:0]/DDR_CLK#[5:0] The clock signal group includes six differential clock pairs per channel. The EP80579 generates and drives these differential clock signals. Since the EP80579 supports both registered and unbuffered DDR2 DIMMs, three separate differential clock pairs are routed to each DIMM connector.
Page 124: Ep80579-To-Dimm Interconnect Ddr2 Clock Signals
BREAK ROUTE The differential clock pairs must be routed differentially from the EP80579 pin to their associated DIMM pins and must maintain the correct isolation spacing from other signals. Additionally, it is important to maintain the correct spacing and length matching between the pair to protect the differential integrity.
Page 125: Ddr2 Point-To-Point Clock Routing Diagram
® Intel EP80579 Integrated Processor Product Line—System Memory Interface (DIMM) Figure 80. DDR2 Point-to-Point Clock Routing Diagram EP80579 EP80579 DIMM EP80579 Pin Differential Board Breakout Package Routing Routing Trace ROUTE BREAK Table 41. Clock Signal Group Routing Guidelines (Sheet 1 of 2)
Page 126: Clock Signal Group Routing Guidelines
DIMMs. The EP80579 supports two single-rank and one dual-rank DIMMs. Always load the DIMM slot farthest from EP80579 first (DIMM 0). DIMM 0 can be populated with either a single-rank or a dual-rank DIMM. DIMM1 supports only a single-rank DIMM.
Page 127: Ddr2 Control Signals- Implementation
® Intel EP80579 Integrated Processor Product Line—System Memory Interface (DIMM) Figure 81. DDR2 Control Signals- Implementation EP80579 VTT_DDR DIMM 0 DIMM 1 Board Breakout Package Routing Routing Trace CKE0 CS0# ODT0 VTT_DDR DIMM2DIMM Routing CKE1 CS1# ODT1 BREAK ROUTE TERM Table 42.
Page 128: Write Operation Odt Table
(TTL of CMD/ADD) + 2.5 in ±5% (See Table BREAK ROUTE TERM ® See the Intel EP80579 Integrated Processor Product Line Datasheet for package length information. Max = 0.8 in BREAK Calculate from Total Trace Length ROUTE Max = 0.8 in •...
Page 129: Read Operation Odt Table
(RAS#), column address select (CAS#), and write enable (WE#). The address/ command signals are “clocked” into the DIMMs using the positive edge of the differential clock signals. The EP80579 drives the address/command and clock signals together. Resistor packs are acceptable for the parallel (R...
Page 130: Address/Command Daisy Chain With Parallel Termination Topology Diagram
Total Trace Length (TTL) = (L 2.0 in - 6.0 in BREAK ROUTE TERM ® See the Intel EP80579 Integrated Processor Product Line Datasheet for package length information. Max = 0.8 in BREAK Max = 4.0 in ROUTE Max = 0.8 in •...
Page 131: Reset Pin Requirement
SSTL_18 signaling levels. The DIMM RESET# input must not go low for any reason once the power up sequence is complete. The EP80579 drives all clock enables low by default as it comes out of power up. The timing of the PWRGOOD signal must be such that EP80579 is safely driving DDR_CKE low when PWRGOOD transitions from low to high.
Page 132: Ddr_Slwcres, Ddr_Rcompx, Ddv_Cres, & Ddr_Cres0 Routing Topology
Figure 84). Intel recommends 20 mil wide traces with a minimum spacing of 12 mils from other signals. When breaking out from the EP80579, maintain a minimum spacing of 4.5 mils spacing up to a maximum length of 500 mils.
Page 133: Ddr_Vref Generation Example Circuit
Vref circuit. Intel recommends at least a 20 mil wide trace with a minimum spacing of 12 mils from other signals. For the best signal integrity, minimize this length as much as possible.
Page 134: Decoupling Recommendations
When designing a board, the following decoupling recommendations should be followed: • Capacitors should be mounted as close to the EP80579 as possible. They should be no further than 10 mm from the edge of the EP80579 package for the DDR2 channel.
Page 135: Pci Express* Interface
2x4 or a 2x1 (PEA0 and PEA1). This interface is referred to throughout this document as the PCI Express Port A (PEA). The EP80579 may be configured as x8; in that case the reference is PEA. The EP80579 may also be configured in x4 mode; in which case there are two available x4 ports referred to as PEA0 and PEA1.
Page 136: Pci Express Layout Design Guidelines
For more information on PCI Express, see the PCI Express Base Specification, Rev. 1.1 and PCI Express Card Electromechanical Specification, Rev. 1.0 or later. The EP80579 provides support for x8 port or x4 port. The x8 port can be divided into two x4 ports or two x1 ports.
Page 137: Board Stack-Up Consideration
® Intel EP80579 Integrated Processor Product Line—PCI Express* Interface Mode conversions are due to imperfections and other trace mismatches on the interconnect which transform differential mode voltage to common mode voltage and vice versa. For example, length mismatch within pairs or an asymmetric via layout could cause mode conversion.
Page 138: Impedance Requirements
® PCI Express* Interface—Intel EP80579 Integrated Processor Product Line Follow the specified stackup in Figure TBD to avoid frequency-dependent loss effects that may occur at PCI Express edge rates. If the dielectric characteristics are different from those specified in the stackup (TBD), the solution space presented in this section may not apply.
Page 139: Ac Coupling Requirements
® Intel EP80579 Integrated Processor Product Line—PCI Express* Interface Figure 88. Recommended PCI Express Microstrip Trace Width/Spacing Non- Non- Interface Interface Differential Differential Signal Signal Pair Pair 4.75 4.75 4.75 4.75 5.25 20 or 3x 5.25 20 or 3x dielectric...
Page 140: Compensation Resistor Signals Guidelines
• L2 is the main routing section that is from the AC blocking capacitor via to the PCI Express connector breakout region. • L3 is the breakout region of the PCI Express connector. • LT is the main routing section that is from the EP80579 pin to the PCI Express connector. ®...
Page 141: Pci Express Connector Routing (Ep80579 Transmit)
• L1 is the EP80579 breakout region. • L2 starts from the edge of the EP80579 breakout region to the PCI Express connector. • LT is the main routing section that is from the EP80579 pin to the connector. ® Intel...
Page 142: Topology 2 - Ep80579 To Pci Express Connector
PCI Express Figure 92 connector on the board with a logic analyzer connector. In this case, EP80579 is a transmitter and the PCI Express connector is a receiver. All traces must be routed on the same layer.
Page 143: Pci Express Connector With Lai Connector Routing (Ep80579 Transmit)
• L5 is from the logic analyzer connector breakout region to the PCI Express connector. • LT is the main routing section that is from the EP80579 pin to the PCI Express connector. Table 51. PCI Express Connector with LAI Connector Routing (EP80579 Transmit)
Page 144: Pci Express Connector With Lai Connector Routing (Ep80579 Transmit)
• L5 is from the logic analyzer connector breakout region to the PCI Express connector breakout region. • LT is the main routing section that is from the EP80579 pin to the PCI Express connector. Table 52. PCI Express Connector with LAI Connector Routing (EP80579 Receive) (Sheet...
Page 145: Topology 3 - Ep80579 To Pci Express Down Device
• L2 is the main routing section that is from the AC blocking capacitor via to the PCI Express device breakout region. • L3 is the breakout region of the PCI Express device. • LT is the main routing section that is from the EP80579 pin to the PCI Express device. ®...
Page 146: Pci Express Down Device Routing (Ep80579 Transmit)
PCI Express on Figure 95 board device. In this case, EP80579 is a receiver and the PCI Express device is a transmitter. LT must be routed on the same layer and the signals must reference one continuous plane.
Page 147: Pci Express Down Device Routing (Ep80579 Receive)
• L2 starts from the EP80579 breakout region to the PCI Express device breakout region. • L3 is the breakout region of the PCI Express device. • LT is the main routing section that is from the EP80579 pin to the PCI Express device. Table 54.
Page 148: Topology 4 - Ep80579 To Pci Express Down Device With Logic Analyzer Connector
• L5 is from the logic analyzer connector breakout region to the PCI Express device break-in region. • L6 is the break-in region of the PCI Express device. • LT is the main routing section that is from the EP80579 pin to the PCI Express device. Table 55.
Page 149: Pci Express Down Device With Lai Connector Routing (Ep80579 Transmit)
• L5 is from the logic analyzer connector breakout region to the PCI Express device break-in region. • L6 is the break-in region of the PCI Express device. • LT is the main routing section that is from the EP80579 pin to the PCI Express device. Table 56.
Page 150: Additional Considerations For Pci Express
® PCI Express* Interface—Intel EP80579 Integrated Processor Product Line Table 56. PCI Express Down Device with LAI Connector Routing (EP80579 Receive) Parameter Routing Guidelines Figure Trace Length L2, L2’ – AC CAP to logic Min = 0.5 in. Figure 97 analyzer breakout region.
Page 151: Pci Express (Jtag) Boundary Scan Pins
10.2.5 Probing Differential Pairs Be aware of limitations when probing the PCI Express Tx pairs on EP80579. There may be a mismatch in impedance caused by the grid pitch and general routing in the breakout region if the Tx probing is done close to the breakout region. In this case, localized reflections may be misread as poor signal integrity.
Page 152: Serial Ata (Sata) Interface
Rx and Tx. Note: The minimum length must be met. That minimizes our Max peak to peak differential voltage (for Gen 2). Properly placing a SATA connector (not too close to the EP80579) ® Intel EP80579 Integrated Processor Product Line...
Page 153: Sata Layout And Routing Example
® Serial ATA (SATA) Interface—Intel EP80579 Integrated Processor Product Line so that serpentining is not necessary would be the approach to meeting the minimum requirement and not serpentining. • Keep SATA traces 20 mils from any vias on the motherboard whenever possible.
Page 154: Sata Transmit And Receive Signals - Sata_Txp[1:0], Sata_Txn[1:0], Sata_Rxp[1:0], Sata_Rxn[1:0]
® Intel EP80579 Integrated Processor Product Line—Serial ATA (SATA) Interface 11.2 SATA Transmit and Receive Signals – SATA_TXp[1:0], SATA_TXn[1:0], SATA_RXp[1:0], SATA_RXn[1:0] The SATA interface has two differential transmit and receive pairs for a total of 8 signals. Route each pair differentially as microstrip or stripline.
Page 155: Sata Tx And Rx Signal Routing Topology
® Serial ATA (SATA) Interface—Intel EP80579 Integrated Processor Product Line Figure 99. SATA Tx and Rx Signal Routing Topology SATA Tx\Rx StriplineTopology _ac_2 _ac_1 Board Break out Board Board (SL) (SL) (MS) (MS) EP80579 AC CAP SATA CONN Break out...
Page 156: Sata Pcb Routing
® Intel EP80579 Integrated Processor Product Line—Serial ATA (SATA) Interface Figure 100. SATA PCB Routing SATA Tx and Rx Stripline PCB Routing Main Board Routing EP80579 Pkg SATA CONN Layer 3 or 8 AC CAP Breakout Microstrip Board Routing NOTE: Breakout\ Breakin descriptions are as follows: 1.
Page 157: Sata Trace Separation
® Serial ATA (SATA) Interface—Intel EP80579 Integrated Processor Product Line 11.2.1 SATA Trace Separation Figure 101 provides an illustration of the recommended trace spacing. Use the following separation guidelines for the SATA interface: • Maintain parallelism between SATA differential signals with the trace spacing needed to achieve 90 Ω...
Page 158: Sata Ac Coupling Requirements
EP80579 and the capacitor on the ‘P’ signal must be identical to the distance between EP80579 and the capacitor on the ‘N’ signal for the same pair.
Page 159: Sataled# Implementation
11.6 SATALED# Implementation EP80579 provides a signal (SATALED#) to indicate SATA device activity. In order for this signal to work in conjunction with Parallel ATA hard drives, it is recommended that designers implement similar glue logic as illustrated in Figure 103.
Page 160: Sata Cable 90º Bend Height Example
® Intel EP80579 Integrated Processor Product Line—Serial ATA (SATA) Interface Figure 104. SATA Cable 90º Bend Height Example 1.5” AREA C Ref. 0.087” 0.087” 0.087” R6.6 1.37” 1.37” 1.37” 1.03” 1.03” 1.03” Figure 105 shows the ATX Specification rev 2.1 height restriction regions. With the...
Page 161: Sata Host Connector Placement Atx Area B
® Serial ATA (SATA) Interface—Intel EP80579 Integrated Processor Product Line Figure 106. SATA Host Connector Placement ATX Area B Place connector at left of card boundary An additional consideration is the relative placement to other SATA host connectors as well as other neighboring parts and devices on the motherboard.
Page 162: Terminating Unused Sata Interface
® Intel EP80579 Integrated Processor Product Line—Serial ATA (SATA) Interface Figure 107. Example of Poor Host Connector Placement Figure 108. Minimum Host Connector Placement Spacing (From SATA Specification) 16.00 mm 16.00 mm 4.00 mm 4.00 mm 7.00 mm 7.00 mm 0.90 mm...
Page 163 ® Serial ATA (SATA) Interface—Intel EP80579 Integrated Processor Product Line — SATA_RXp[1:0], SATA_RXn[1:0], SATA_TXp[1:0], SATA_TXn[1:0], and SATA_LED#. • VCCAPLL must be connected directly to VCC1_2, but the filter caps are not required. • Disable the SATA function via the system BIOS. See the description for the Function ®...
Page 164: Universal Serial Bus (Usb) Interface
12.1 USB Interface The EP80579 contains one Enhanced Host Controller Interface (EHCI) USB 2.0 and one Universal Host Controller Interface (UHCI). The EP80579 supports a maximum of two USB ports, which can be configured independtly as either EHCI or UHCI. The...
Page 165: Usb Differential Signals - Usbp[1:0], Usbn[1:0]
See Section 12.7, “Front Panel Solutions” on page 173 for more information about front panel solutions. Table 60. Case 1, USB Routing Guidelines – EP80579 to Connector (Sheet 1 of 2) Parameter Routing Guidelines Figure Signal Group USBp[1:0], USBn[1:0]...
Page 166: Usb Trace Lengths From Controller To Connector
Figure 109. USB Trace Lengths From Controller to Connector LT = L1 + L2 EP80579 Choke Connector Table 61. Case 2, USB Routing Guidelines – EP80579 Front Panel Option (Sheet 1 of 2) Parameter Routing Guidelines Figure Signal Group USBp[1:0], USBn[1:0]...
Page 167: Usb Trace Lengths For Ep80579 Front Panel Solution
® Universal Serial Bus (USB) Interface—Intel EP80579 Integrated Processor Product Line Table 61. Case 2, USB Routing Guidelines – EP80579 Front Panel Option (Sheet 2 of 2) Parameter Routing Guidelines Figure Length matching over LT within a pair is 60 mils or less Length Tuning Requirements Segment length matching, L1 to L1’, L2 to L2’, and L3...
Page 168: Usb Trace Lengths For Optional Front Panel Option
® Intel EP80579 Integrated Processor Product Line—Universal Serial Bus (USB) Interface Figure 111. USB Trace Lengths For Optional Front Panel Option EP80579 Header 12.2.2.1 USB 2.0 Trace Separation Use the following separation guidelines (Figure 112 Figure 113 show the recommended trace spacing): •...
Page 169: Usb_Rbiasp/Usb_Rbiasn Connection
The trace length on front panel daughter card has a maximum trace length of 2 inches. c. USB twisted-pair shielded cable as specified in the USB 2.0 Specification was used. For front panel solutions, signal matching is considered from EP80579 to the front panel header. 12.2.3...
Page 170: Clock Signal -- Usb Clk48
® Intel EP80579 Integrated Processor Product Line—Universal Serial Bus (USB) Interface Table 64. USB_RBIASp/USB_RBIASn Routing Summary Trace USB_RBIASp/USB_RBIASn Maximum Trace Signal Length Signal Impedance Routing Requirements Length Matching Referencing Short USB_RBIASp and A = 0.50 inch 50 Ω ±15% USB_RBIASn pins at the (EP80579 to Resistor) package.
Page 171: Gnd Plane Splits, Voids, And Cut-Outs (Anti-Etch)
® Universal Serial Bus (USB) Interface—Intel EP80579 Integrated Processor Product Line 12.3.2 GND Plane Splits, Voids, and Cut-Outs (Anti-Etch) Avoid anti-etch on the GND plane. 12.4 USB Power Line Layout Topology The following is a suggested topology for power distribution of Vbus to USB ports.
Page 172: Esd
Figure 116. Other types of low-capacitance ESD protection devices may work as well, but were not investigated. As with the common mode choke solution, Intel recommends designers include footprints for some type of ESD protection device as a stuffing option in case it is needed to pass ESD testing.
Page 173: Front Panel Solutions
® Universal Serial Bus (USB) Interface—Intel EP80579 Integrated Processor Product Line 12.7 Front Panel Solutions 12.7.1 Internal USB Cables The front panel internal cable solution must meet all the requirements of Chapter 6 in the USB 2.0 Specification for high/full-speed cabling for each port with the exceptions described in Section 12.7.1.2, “Internal Cable Option 2”...
Page 174: Motherboard/Pcb Mating Connector
® Intel EP80579 Integrated Processor Product Line—Universal Serial Bus (USB) Interface Table 65. Conductor Resistance (Table 6-6 from USB 2.0 Specification ) American Wire Gauge Ohm/100 Meters (AWG) Maximum 23.20 14.60 9.09 5.74 3.58 Example: Two 24-gauge (AWG) power or ground wires can be replaced with one 20- gauge wire.
Page 175: Front Panel Header Schematic
Vbus No connect or over- current sense Intel highly recommends that the fuse element (thermistor) for the front panel header be included on the motherboard to protect the motherboard from damage, for the following reasons: • protects the motherboard from damage in the case where an un-fused front panel cable solution is used.
Page 176: Front Panel Daughter Card
® Intel EP80579 Integrated Processor Product Line—Universal Serial Bus (USB) Interface 12.7.2.2 Routing Considerations Keep the following routing considerations in mind: • Traces or surface shapes from Vcc to the thermistor, to C , and to the BYPASS connector power and ground pins must be at least 50 mils wide to ensure adequate current carrying capability.
Page 177 ® Universal Serial Bus (USB) Interface—Intel EP80579 Integrated Processor Product Line • USBp[1:0], USBn[1:0] - These signals have integrated 15kW pull-down resistors. Unused USB ports can be left as no connect. • OC[1:0]# - If these signals are not used, pull them up to VCCPSUS with an 10 kΩ...
Page 178: System Management Bus (Smbus) Interface
(SPD) on RAM, thermal sensors, etc. The slave interface allows an external microcontroller to access system resources. The EP80579 consists of a host/slave controller and a slave controller, both of which are I C compliant.
Page 179: General Design Considerations
C transaction, in which the device is sending information to EP80579, the device may not release the SMBus if EP80579 receives an asynchronous reset. By using the core power, the BIOS is able to reset the device if necessary. SMBus 2.0- compliant devices have a time-out capability that makes them insusceptible to this C issue, allowing flexibility in choosing a voltage supply.
Page 180: Calculating The Physical Segment Pull-Up Resistor
69. The Development Board does not support this feature. This feature can be custom design to consider add the BMC connector for an add in the BMC card. Intel did not validate this solution on the Development Board. A list of system management features appears below...
Page 181: Enabled System Management Vendors (Optional)
IPMI system event log (SEL), Field Replacement Unit log (FRU), and pre-boot/BIOS boot process. • Power failure The system management can monitor the powergood signals on EP80579 to detect power subsystem failure. • System reset The reset button on the front panel is routed through the BMC, allowing the BMC to monitor and control reset to possibly prevent reset from occurring.
Page 182: Development Board System Management Implementation
® Intel EP80579 Integrated Processor Product Line—System Management Bus (SMBus) Interface Table 69. Enabled System Management Vendors Vendor Info Agilent Technologies* N2523A, N2532A, N2531A http://www.agilent.com/find/rmc American Megatrends* http://www.ami.com/ National Semiconductor* NSC PC87431, PC87435, PC87436 http://www.national.com/ OSA Technologies* http://www.osatechnologies.com/ Phoenix Technologies Ltd.* http://www.phoenix.com/...
Page 183: Development Board System Management - Smbus Block Diagram
3 C lock EP80579’s SMBus has many features for system management. The following sections show an example implementation of system management portions of EP80579 in the Development Board. The system platform may use a BMC on a separate system management card, although this is not part of the Development Board implementation.
Page 184: Sio Implementation
® Intel EP80579 Integrated Processor Product Line—System Management Bus (SMBus) Interface 13.4.1 SIO Implementation The System Management interface requires access to a serial port for out-of-band operation and for alerts. The SMC can have its own dedicated UART and COM port on the baseboard or it can be wired to share system resources.
Page 185: System Management Sio Implementation
SMC_CLR_CMOS# SMC_SPKR# Notes: 1. This is an example for the EP80579 SMBus interface implementation in the EP80579 Development Board. This diagram idoes not present every signal. See the EP80579 Development Board schematics for more details. 2. The Optional BMC connection is not implemented in the EP80579 Development Board.
Page 186: Low Pin Count (Lpc) Interface
• LPCPD# (suspend status and LPC power down) is connected to the EP80579 SUS_STAT#. • LSMI# may be connected to any of the EP80579 GPIO signals, as they may be configured as inputs to generate an SMI#. • Connecting the Super I/O PME# to the PME# signal is possible. A better choice is to connect it to one of the GPIO signals, as they may be configured to generate an SCI.
Page 187: Lpc Layout
• No 90-degree bends or stubs. 14.2.2 LPC Interface Routing and Topology This section provides guidelines for topology routing. The Development Board provides four basic component devices connected to the EP80579’s LPC interface. These devices include: • port 80 • Firmware Hub •...
Page 188: Development Board Lpc Interface Block Diagram
• Daisy chain all signals to every device on the bus • Use a total of five or fewer devices on the LPC bus • The EP80579 can be placed anywhere in the bus daisy chain (can be in the middle or at the end of the chain) •...
Page 189: Clock Signals -- Clk33
The TPM is a device that resides on the motherboard and is connected to EP80579 using the Low Pin Count (LPC) bus to communicate with the rest of the board.
Page 190: Motherboard Placement Consideration
14.3.3 Motherboard Placement Consideration Optimum routing can typically be achieved by placing the TPM close to the EP80579 or other LPC peripherals (e.g., Firmware Hub, Super I/O). The TPM is a security device that must be shielded as much as possible from physical access.
Page 191: Firmware Hub (Fwh) Guidelines
The FWH INIT# signal trip points need to be considered because they are NOT consistent among different FWH manufacturers. The INIT# signal is active-low. Therefore, the inactive state of the EP80579 INIT33V# signal needs to be at a slightly higher value than the V min FWH INIT# pin specification.
Page 192: Fwh Vpp Isolation Circuitry
® Intel EP80579 Integrated Processor Product Line—Low Pin Count (LPC) Interface the life of the device). The V of 12V would be useful in a programmer environment, which is typically an event that occurs very infrequently (much less than 80 hours). The pin must be connected to 3.3V on the motherboard.
Page 193: Real Time Clock (Rtc) Interface
This input is amplified and driven back to the crystal circuit via the RTCX2 signal. Internal to the EP80579, the RTCX1 signal is amplified to drive internal logic as well as generate a free-running, full-swing clock output for system use. This output signal of...
Page 194: External Capacitors
= crystal’s load capacitance. This value can be obtained from the crystal load specification. • C = input capacitances at the RTCX1 and RTCX2 signals of EP80579. These ® values can be obtained from the Intel EP80579 Integrated Processor Product Line Datasheet.
Page 195: Rtc Layout Considerations
Example: According to the required 12.5 pF load capacitance of a typical crystal that is used with ° EP80579, the calculated values of C1 = C2 is 15 pF at room temperature (25 C) yields a 32.768KHz oscillation. °...
Page 196: Rtc External Battery Connection
RTC voltage is in the range of 3.0V to 3.3V. The battery must be connected to EP80579 via an isolation Schottky diode circuit. The Schottky diode circuit allows the RTC well to be powered by the battery when the system power is not available and the system power when it is available.
Page 197: Internal Only Rtc External Rtest# Circuit
® Intel EP80579 Integrated Processor Product Line—Real Time Clock (RTC) Interface 15.1.5 Internal only RTC External RTEST# Circuit Figure 132. RTEST# External Circuit for the RTC VCCPSUS DIODE/ BATTERY CIRCUIT VCCPRTC 1.0 μF 1 kΩ 20 kΩ RTEST# 1.0 μF...
Page 198: Rtc Well Input Strap Requirements
® Real Time Clock (RTC) Interface—Intel EP80579 Integrated Processor Product Line 15.1.7 RTC Well Input Strap Requirements All RTC-well inputs (RTEST#, INTRUDER#) recommend be either pulled up to VCCPRTC or pulled down to ground while in the G3 state. RTEST#, when configured as shown in Figure 132 meets this requirement.
Page 199: Synchronous Peripheral Interface (Spi)
16.0 Synchronous Peripheral Interface (SPI) The EP80579’s Serial Peripheral Interface (SPI) is a 4-pin interface that provides a potentially lower-cost alternative for system flash versus the Firmware Hub on the LPC bus. The Serial Peripheral Interface is used to support only one SPI compatible flash device - only one chip select is available.
Page 200: Spi Routing Guidelines
SPI_CLK 1. W represents width of signal; S represents spacing to any other signal. 2. R1 = 15Ω and should be placed 0.1-1” from the EP80579. 3. R2 = 15Ω and should be placed 0.1-1” from the serial flash device.
Page 201: Serial Flash Vendors
OEMs must fully validate any SPI flash device to ensure compatibility with their platforms. This list should not be considered as a complete list of SPI vendors and is not an indication of Intel approved devices or vendors. Contact your preferred flash vendor directly to determine if they have a compatible device.
Page 202: General Purpose I/O (Gpio) And Interrupt Interface
Interface 17.1 GPIO Signals The EP80579 provides 36 general-purpose input/output (GPIO) pins for use in generating and capturing application-specific input and output signals. By design, each GPIO pin is hard-wired as input (GPI), output (GPO), or input/output (GPIO). Only the Input/Output (GPIO) pins can be re-programmed as an input or output.
Page 203: Development Board Gpio Usage
® General Purpose I/O (GPIO) and Interrupt Interface—Intel EP80579 Integrated Processor Product Line Table 75. GPIO Pin Definitions (Sheet 2 of 2) I/O Type Function Alternate Signal(s) (Default (Default Description Mode Mode) Mode) GPIO[27] GPIO IRQ39 Multiplexed with IOAPIC IRQ39...
Page 204: Interrupts
FPGA_OUT_5 17.2 Interrupts EP80579 provides support for up to four PCI interrupt pins (PIRQ[E:H]) and PCI 2.3 message-based interrupts. EP80579 also maintains support for ISA (legacy)-style interrupts via the serial interrupt protocol (SERIRQ). PCI Interrupts (PIRQ[A:D]) are not pinned out on EP80579, but supported via SERIRQ. When IOAPIC is active, IRQ[39:24] are externally driven interrupts through GPIO pins, enabled if SIU_TXD2 is pulled low on power-up.
Page 205 ® General Purpose I/O (GPIO) and Interrupt Interface—Intel EP80579 Integrated Processor Product Line Table 77. Interrupt Configurations - APIC Mode (Sheet 2 of 2) Interrupt IRQ # Source Pin Name Name External GPIO[17] External GPIO[20] External GPIO[21] External GPIO[23] External...
Page 206: Serial Interface Unit (Siu/Uart)
Serial Interface Unit (SIU/UART) 18.1 SIU (UART) Interface The EP80579 provides two asynchronous Serial I/O Unit (SIU/UART) ports. These SIUs are 16550-compliant with 16-byte transmit and receive buffers. Both SIUs are full-function and can be used for debug purposes or connected to an external modem.
Page 207: Siu Interface Interconnect
® Serial Interface Unit (SIU/UART)—Intel EP80579 Integrated Processor Product Line Table 78. SIU Interface Signals (Sheet 2 of 2) Signal Name Description Direction DATA SET READY for UART1 and UART2: [Active low]. This pin indicates that the external agent is ready to communicate with UART.
Page 208: Siu Interface Interconnect
® Intel EP80579 Integrated Processor Product Line—Serial Interface Unit (SIU/UART) Figure 134. SIU Interface Interconnect EP80579 Connector (Female) SIU_DCD# SIU_DSR# 1 DCD 2 RXD SIU_RXD 3 TXD SIU_RTS# RS-232 4 DTR SIU_TXD# Transceiver 5 GND 6 DSR SIU_CTS# 7 RTS...
Page 209: Gigabit Ethernet (Gbe) Interface
2.5V drivers that are 3.3V-tolerant. This is a violation of the RMII specification, which calls for TTL level outputs (not LVTTL) and 5V input level tolerance. We expect all major PHY devices that may be used in a EP80579 system will drive a maximum voltage of 3.3V.
Page 210: Gbe Mac Interface Guidelines
® Gigabit Ethernet (GbE) Interface—Intel EP80579 Integrated Processor Product Line 19.2 GbE MAC Interface Guidelines The GbE design guidelines provided in this chapter apply only to the interface between the GbE MAC interface and the LAN PHY component. See the LAN component’s...
Page 211: Gben Pin Table
• GBE Port 0 supports Wake-On-LAN (WOL); hence GBE Port 0 Block resides in the Sustain Power Well within EP80579. It is required that all GBE Port 0 (Transmit/Receive) interface signals on the platform be powered by GBE Standby Voltage. GBE Port 1&2 should be powered by GBE core power.
Page 212 • GBEn_TxDATA[3:0] signal name is GBEn_TxDATA[7:4] on the falling edge of GBEn_TxCLK when GBEn_TxCTL is active. • Pull up GBE Port 0 Receive Data signals to EP80579 2.5V Standby Voltage (VCCSUS25) using a 1.2KΩ ± 5% resistors. • Pull up GBE Port 1&2 Receive Data signals to GBE 2.5V using a 1.2KΩ ±...
Page 213 Start Frame Delimiter (SFD) and excluding any End-of-Frame delimiter. • Pull up GBE Port 0 Receive Control signal to EP80579 2.5V Standby Voltage (VCCSUS25) using a 1.2KΩ ± 5% resistor. • Pull up GBE Port 1&2 Receive Control signals to GBE 2.5V using a 1.2KΩ...
Page 214 • GBEn_RxDATA[3:0] signal name is GBEn_RxDATA[7:4] on the falling edge of GBEn_RxCLK when GBEn_RxCTL is active • Pull up GBE Port 0 Receive Data signals to EP80579 2.5V Standby Voltage (VCCSUS25) using a 1.2KΩ ± 5% resistors. • Pull up GBE Port 1&2 Receive Data signals to GBE 2.5V using a 1.2KΩ ±...
Page 215: Gbe Interface - Lan Connect Interface Guidelines
± 5% resistor. MDIO Note: • Must be pulled high through a 10 KΩ resistor to EP80579 GbE 2.5V Standby (VCCSUS25) the interface is not used. • Management Data Clock. • Provide termination if signal is connected to multiple receivers •...
Page 216: Gbe Ethernet Interface - Rmii Mode
® Gigabit Ethernet (GbE) Interface—Intel EP80579 Integrated Processor Product Line The RGMII interface gets Rx clock from the PHY and Tx clock from the MAC. The PHY receives a 25 MHz reference clock from the board, and the PHY sources the 125 MHz reference clock to the MAC.
Page 217: Gbe Rmii Mode Signal Connection Block Diagram
® Intel EP80579 Integrated Processor Product Line—Gigabit Ethernet (GbE) Interface Figure 137. GbE RMII Mode Signal Connection Block Diagram RMII signals GBEn MAC 100/ 10 Base PHY GBEn_TxCTL TX_EN GBEn_TxDATA[1:0] TXD_[1:0] CRS_DV GBEn_RxCTL RX_ER GBEn_RxDATA[3] RXD[1:0] GBEn_RxDATA[1:0] VCCGBEPSUS 1.5 Kohm...
Page 218: Gbe Transmit And Receive Topology
® Gigabit Ethernet (GbE) Interface—Intel EP80579 Integrated Processor Product Line 19.6 GbE Transmit and Receive Topology 19.6.1 GbE Transmit Topology 19.6.1.1 GbE Transmit Clock Topology Figure 138 shows the routing topology of the GbE Transmit clock. The transmit clock topology is for the routing of GbEn_TxCLK (RGMII) or GbEn_CLK (RMII). The routing guidelines for the Transmit Data and Transmit Control signals in section Section 19.6.1.2...
Page 219: Gbe Rgmii Transmit Path Clock Topology
® Intel EP80579 Integrated Processor Product Line—Gigabit Ethernet (GbE) Interface Figure 138. GbE RGMII Transmit Path Clock Topology RGMII Transmit Path Clock Topology (EP80579 PHY) Pull_up V2P5 Rpull_up Pull_Up TL (μs) EP80579 Break out Board Break in Transmitter Receiver (Clock)
Page 220: Gbe Rgmii Transmit Path Clock Routing Guidelines
® Gigabit Ethernet (GbE) Interface—Intel EP80579 Integrated Processor Product Line Table 83. GbE RGMII Transmit Path Clock Routing Guidelines Parameter Routing Constraints Routing Layer Stripline Microstrip Reference Plane Ground Reference Board Trace Impedance 55 Ω 55 Ω Trace Width 3.75mils (L3/L8) 4.5mils (L1/L10)
Page 221: Gbe Rgmii Transmit Path Data\Control Topology
® Intel EP80579 Integrated Processor Product Line—Gigabit Ethernet (GbE) Interface Figure 139. GbE RGMII Transmit Path Data\Control Topology RGMII Transmit Path Data\Control Topology (EP80579 PHY) Pull_up V2P5 Rpull_up Pull_Up TL (μs) EP80579 Break out Board Break in Transmitter Receiver (Data\Ctrl)
Page 222: Gbe Receive Topology
® Gigabit Ethernet (GbE) Interface—Intel EP80579 Integrated Processor Product Line Table 84. GbE RGMII Transmit Path Data\Control Routing Guidelines Parameter Routing Constraints Routing Layer Stripline Microstrip Reference Plane Ground Reference Board Trace Impedance 55 Ω 55 Ω Trace Width 3.75mils (L3/L8) 4.5mils (L1/L10)
Page 223: Gbe Rgmii Receive Path Clock Topology
® Intel EP80579 Integrated Processor Product Line—Gigabit Ethernet (GbE) Interface Figure 140. GbE RGMII Receive Path Clock Topology RGMII Receive Path Clock Topology (EP80579 PHY) Pull_up V2P5 Rpull up Pull Up TL (μs) EP80579 Break in Board Break out Receiver...
Page 224: Gbe Rgmii Receive Path Clock Routing Guidelines
® Gigabit Ethernet (GbE) Interface—Intel EP80579 Integrated Processor Product Line Table 85. GbE RGMII Receive Path Clock Routing Guidelines Parameter Routing Constraints Routing Layer Stripline Microstrip Reference Plane Ground Reference Board Trace Impedance 50 Ω 50 Ω Trace Width 4.5mils (L3/L8) 5.5mils (L1/L10)
Page 225: Gbe Rgmii Receive Path Data/Clock/Control Topology
® Intel EP80579 Integrated Processor Product Line—Gigabit Ethernet (GbE) Interface Figure 141. GbE RGMII Receive Path Data/Clock/Control Topology RGMII Receive Path Data\Control Topology (EP80579 PHY) Pull_up V2P5 Rpull up Pull Up TL (μs) EP80579 Break in Board Break out Receiver...
Page 226: Gbe Serial Eeprom
® Gigabit Ethernet (GbE) Interface—Intel EP80579 Integrated Processor Product Line Table 86. GbE RGMII Receive Path Data\Control Routing Guidelines Parameter Routing Constraints Routing Layer Stripline Microstrip Reference Plane Ground Reference Board Trace Impedance 50 Ω 50 Ω Trace Width 4.5mils (L3/L8) 5.5mils (L1/L10)
Page 227: Crosstalk Considerations
® Intel EP80579 Integrated Processor Product Line—Gigabit Ethernet (GbE) Interface The resistive mechanism on those I/O pads references external resistors that the user provides to optimize the signal impedance termination. Thus the output driver impedance can be tuned specifically to the application PCB characteristics for nominal signal transfer into the transmission lines formed by the PCB traces.
Page 228 ® Gigabit Ethernet (GbE) Interface—Intel EP80579 Integrated Processor Product Line • Gigabit Ethernet signals must be ground referenced. • Route all traces over continuous GND planes, with no interruptions. Avoid crossing over anti-etch if at all possible. Any discontinuity or split in the ground plane can cause signal reflections and must be avoided.
Page 229: Ieee 1588-2008 Hardware Assist Interface
The main objective of IEEE 1588-2008 is to accurately synchronize independent clocks, running on separate nodes of a network, to a grandmaster clock. The EP80579 provides hardware assist for GbE0, GbE1, CAN0, CAN1 and the two auxiliary input signals, master and slave mode. The master device holds the grandmaster clock and the slaves synchronize to the master.
Page 230: Input/Output Signal Application
® IEEE 1588-2008 Hardware Assist Interface—Intel EP80579 Integrated Processor Product Line Figure 142. Classic Clock Synchronization Example NETWORK NETWORK IEEE-1588 NO IEEE-1588 ASSIST Full Duplex NODE 1 NODE 2 NODE 3 NODE 1 NODE 2 NODE 3 3:00 AM 3:03 AM...
Page 231 Figure 143 shows the internal architecture of IEEE 1588-2008 hardware assist implementation in the EP80579. It also shows the various internal registers within the block, such as the System Time Clock register, which contains the system time used for time stamping and triggering events that can be used to drive outputs. Examples of these conditions are: •...
Page 232: Ep80579 Ieee 1588-2008 Hardware Assist Block Diagram
® IEEE 1588-2008 Hardware Assist Interface—Intel EP80579 Integrated Processor Product Line Figure 143. EP80579 IEEE 1588-2008 Hardware Assist Block Diagram TARGET TIME INTERRUPT 64-bit REGISTER AND CONTROL LOGIC WHEN SYSTEM TIME > = TARGET TIME INTERRUPT AUXILIARY TARGET ACCUMULATOR AUX TARGET TIME...
Page 233: Input
® Intel EP80579 Integrated Processor Product Line—IEEE 1588-2008 Hardware Assist Interface 20.1.1 Input Two input pins, AMMSSIG and ASMSSIG, connect to the IEEE 1588-2008 hardware module. These signals can be used to detect status change of events that will require a timestamp for tracking purpose.
Page 234: Controller Area Network (Can) Interface
This is done to overcome the signal delay in the network topology as the signals move through the twisted pair and experience delays. The EP80579 supports two CAN controllers with IEEE 1588-2008 Hardware Assist. The controller requires an external physical interface (CAN driver), therefore this section provides an example of how to connect an external CAN driver.
Page 235: Input/Output Signal Application
® Controller Area Network (CAN) Interface—Intel EP80579 Integrated Processor Product Line Figure 144. CAN Physical Interface Example Connector EP80579 1 RESERVE Transceiver 2 CAN_L CAN_TXD CANH 3 CAN_GND CAN_RXD CANL 4 RESERVED 5 CAN_SHLD CAN_TXEN_N 6 GND DIFFERENTIAL SIGNAL. 7 CAN_H...
Page 236: Multipoint Topology
® Intel EP80579 Integrated Processor Product Line—Controller Area Network (CAN) Interface CNTXD and CNRXD are used to transmit and receive signals, which are relatively low speed, up to 1 MHz. The only signal that requires special attention is CNTXEN; this signal requires a series damping resistor.
Page 237: Local Expansion Bus (Leb) Interface
22.0 Local Expansion Bus (LEB) Interface The EP80579 Local Expansion Bus (LEB) is a flexible, general purpose communication interface between the EP80579 and external peripherals. LEB is specifically designed for compatibility with Intel and Motorola*-style microprocessor interfaces, as well as Texas Instruments* DSP standard Host-Port Interfaces* (HPI).
Page 238: Leb Memory Size (Leb_Size) Strapping
Only 8 chip selects are supported; the other 8 are alias of the first 8 chip selects. Refer to the Utilizing the Local Expansion Bus on the Intel® EP80579 Integrated Processor Product Line Application Note, Document Number 321096 for details.
Page 239: Chip Select Topologies
® Intel EP80579 Integrated Processor Product Line—Local Expansion Bus (LEB) Interface Figure 146. Multi-drop Topology Diagram EP80579 EX_CS[7:0]# EX_CS7# EX_CS6# EX_CS5# EX_CS4# EX_CS3# EX_CS2# BUFFER EX_CS1# EX_CS0# EX_DATA EX_ADDR EX_RD# EX_WR# MEZZ STRATA STRATA COMPACT MEZZ MEZZ FPGA FLASH #1...
Page 240: Chip Select Point-To-Point Topology Diagram
® Local Expansion Bus (LEB) Interface—Intel EP80579 Integrated Processor Product Line Figure 147 Table 89 indicate min and max trace lengths that can be used when routing chip select signals. Figure 147. Chip Select Point-to-Point Topology Diagram Chip Select Point-to-Point Topology...
Page 241: Address Star Topologies
22.3.2.1 Chip Select Address Allocation The LEB occupies 256 MB of address space in the EP80579 Memory Map. Each of the eight chip selects in the LEB has been allocated 32 MB of addressing space which can be individually programmed through the Timing and Control register. For a complete description of the chip select functionality, see the Local Expansion Bus Controller in the ®...
Page 242: Data And Control Star Topology
22.3.4.1 Adding Delay to EX_RD# The EP80579 requires a 2nSec (min) read hold time (Trdhold) on the data bus when reading external devices connecting to the LEB interface. Some of the external devices are able to meet the requirement but many of them do not.
Page 243: Data, And Control Signals Star Topology Diagram
EX_RD# signal with a chip multilayer delay line. The Development Board design uses LDH32 2.5 nSec delay line to meet the EP80579 requirement of Trdhold=2nSec. Note: By delaying the EX_RD#, you also must ensure that the Trdsetup still is valid. Normally this is not a problem since the data becomes valid and is available early in time to allow the to met setup.
Page 244: Mezzanine Card Interconnect
® Local Expansion Bus (LEB) Interface—Intel EP80579 Integrated Processor Product Line Table 90. Address, Data and Control Star Topology Routing Guidelines Parameter Routing Constraints Routing Layer Stripline Microstrip Reference Plane Ground Referenced Board Trace Impedance 50 Ω 50 Ω Trace Width 4.5mils (L3/L8)
Page 245: Address, Data, And Control Signals Mezzanine Star Topology Diagram
® Intel EP80579 Integrated Processor Product Line—Local Expansion Bus (LEB) Interface Figure 150. Address, Data, and Control Signals Mezzanine Star Topology Diagram Address, Data and Control Star Topology (Buffer Mezzanine) MEZZ #1 MEZZ #3 MEZZ #2 BUFFER Break out ADDR...
Page 246: Input/Output Signal Application
• Can be left NC when the interface is not connected to an interfacing device or not used. • Bus Read Note: The EP80579 requires a 2 nSec hold time during read accesses. Requires to delay EX_RD# EX_RD# signal if the interfacing device cannot meet the Thold=2nSec time required by the EP80579.
Page 247: Design Notes
® Intel EP80579 Integrated Processor Product Line—Local Expansion Bus (LEB) Interface Output • Address Latch Enable EX_ALE • Can be left NC when the interface is not connected to an interfacing device or not used. • Chip Selects 0 to 7 •...
Page 248: Time Division Multiplex (Tdm) Interface
TDM encoding. Data moves through the TDM port, in both directions from the SLIC/CODEC to the EP80579 TDM or from the EP80579 to the SLIC/CODEC. The device also requires configuration and control service, which is normally done via the Synchronous Serial Port (SSP) interface.
Page 249: Tdm To Slic/Codec Interface Example
® Time Division Multiplex (TDM) Interface—Intel EP80579 Integrated Processor Product Line Figure 151. TDM to SLIC/CODEC Interface Example VCC3 (3.3 V) EP80579 10 KΩ GPIO_16 GPIO_x External Oscillator SSP Interface 7.2 KHz SSP_EXTCLK to 3.6864 MHz RESET_N SSP_TXD SSP_RXD SSP_SFRM...
Page 250: Input/Output Signal Application
® Intel EP80579 Integrated Processor Product Line—Time Division Multiplex (TDM) Interface 23.3.1 Input/Output Signal Application The TDM controller has a total of 6 input/output signals per TDM port, as shown in the following tables: Inputs/Output • Transmit Frame Channel 0, 1 and 2 •...
Page 251: Synchronous Serial Port (Ssp) Interface
HSS port. 24.2 EP80579 SSP Interface The EP80579 SSP interface has a total of five input/output signals. These signals can be configured to the various hardware protocols supported by the SSP port. The following tables show the five pins supported: Inputs •...
Page 252: Serial Peripheral Interface (Spi)
® Synchronous Serial Port (SSP) Interface—Intel EP80579 Integrated Processor Product Line Outputs • Serial Clock SSP_SCLK • Can be left NC when the port is not connected to an interfacing device. • Transmit Data SSP_TXD • Can be left NC when the port is not connected to an interfacing device.
Page 253: Microwire* Interface
® Intel EP80579 Integrated Processor Product Line—Synchronous Serial Port (SSP) Interface Figure 152. SSP to Serial Flash Interface Example EP80579 Serial Flash SSP_SCLK SSP_SFRM CS_N SSP_TXD SSP_RXD SPI Interface SSP_EXTCLK 7.2 - 3.6864 MHz SSP Interface EXTERNAL OSCILLATOR Note: SSP Clock can be selected from an internal or external source.
Page 254: Sideband Signals
Signal Name Group Description CPU Sleep: • This EP80579 output signal is made visible to the platform for debug purposes only. This internal EP80579 signal places the processor into a state that saves substantial power compared to the Stop- Grant state. When EP80579 is in this state, it does not recognize snoops or interrupts.
Page 255 • This signal should be pulled-down to GND using 10KΩ ± 5% resistor. System Management Interrupt: • This EP80579 output signal is made visible to the platform for debug purposes only. This internal EP80579 signal is active low output synchronous to PCICLK that is asserted in response to one of many enabled hardware or software events.
Page 256 • This signal can be left as a no connect (NC) if not used CPU Power Good: • This EP80579 output signal is made visible to the platform for debug purposes only. This signal is an open drain signal, and requires an external pull-up resistor.
Page 257: Cpuslp_Out#, Init33V_Out#, Nmi, Smi_Out#, Stpclk_Out, Rcin
SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (for example, NMI) by EP80579. The CPU keeps IERR# asserted until the assertion of INIT33V_OUT# or EP80579 is reset IERR# CPU Sideband Output using SYS_RESET#.
Page 258: Debug Port Design Guide
Note: The ITP-XDP and ITP-XDP2 are run-control tools created by Intel® Corporation. They are not sold publicly by Intel. In this document, the term ITP and ITP-XDP can be interchanged with “run-control tool.” Intel works with several run-control tool vendors to create tools that can be used for design (the guidelines presented within this document must also be followed).
Page 259: General Debug Port Overview
26.2.3 Depopulating XDP for Production Units At some point there may be a desire to remove the XDP from production units. Intel recommends that the debug-port real estate and pads remain in place if they need to be populated for a future problem.
Page 260: General Guidelines
® Intel EP80579 Integrated Processor Product Line—Debug Port Design Guide 26.2.4 General Guidelines For some signals, the existence of on-die termination (ODT) within the processor or chipset will remove parts from the platform design. The processor or chipset-specific Thermal Design Specification will clarify if ODT exists on signals for this guideline.
Page 261: Routing Guidelines
This section provides implementation details specific to these designs only and takes priority over any discrepancies existing between this document and any other Debug Port Design Guide. For EP80579 systems, VTAP refers (within this section) to the 1.2V EP80579 core voltage. 26.3.1 JTAG Routing Guidelines 26.3.1.1...
Page 262: Observation Port Routing Guidelines
26.3.1.2 TCK0 and TCK1 Routing Route TCK0 to the EP80579 TCK with a 51 ohm 5% resistor to GND at the EP80579 end. The trace length must be a maximum of 1.5ns. Any stub on this net must be shorter than 200ps.
Page 263: Hook Pins Routing Guidelines
Route point-to-point from the XDP debug port to a 100 ohm resistor on the platform located within 1 inch of the EP80579 input pin. The other side of the 100 ohm resistor is connected to an active LOW enable quickswitch such as the SN75CBTLV1G125 or equivalent.
Page 264 RESET#. The run-control tool uses this signal to sense when a system reset has occurred. Route the EP80579 RESET# signal to the XDP RESET# pin through a 1k ohm isolation resistor. Routing of this signal, before the isolation resistor, is left to the system designers as part of the system design guides.
Page 265: C (Sda/Scl) Routing Guidelines
Specific plating types, locking clips, and alignment pins versions of this connector can be obtained from Samtec*. Table 95 documents the pinout for ITP-XDP connector. Table 95. XDP To EP80579 Signal Connections (Sheet 1 of 2) Target XDP Signal Target XDP Signal Name Device...
Page 266: Mechanical Specifications
® Intel EP80579 Integrated Processor Product Line—Debug Port Design Guide Table 95. XDP To EP80579 Signal Connections (Sheet 2 of 2) Target XDP Signal Target XDP Signal Name Device Device Signal Name Signal System System OBSDATA_A[0] BPM3 EP80579 OBSDATA_C[0] Open...
Page 267: Xdp Connector System Keep-Out Diagram
The placement of the XDP connector on the secondary side should be avoided if possible. Among other reasons, it should be avoided due to the complexity of hand placing and soldering the device. Cap all vias near the XDP-connector pads in compliance with the Intel DFM Guidelines for capped vias. ® Intel...
Page 268: Layout Checklist
Layout Checklist The layout checklist provides design considerations that should be reviewed prior to completing the layout and routing of EP80579-based platform designs. See the individual peripheral interface chapters in this document for more detailed routing guidelines for the platform board.
Page 269: Layout Checklist
® Layout Checklist—Intel EP80579 Integrated Processor Product Line 27.2 Layout Checklist Table 97. Layout Checklist (Sheet 1 of 13) Trace Geometry and Signal Name Length Requirements Comments Impedance IA-32 core Interface Global Clock Unit (CRU) Ω Zdiff = 100 +/- 10% Trace Width –...
Page 270 ® Intel EP80579 Integrated Processor Product Line—Layout Checklist Table 97. Layout Checklist (Sheet 2 of 13) Trace Geometry and Signal Name Length Requirements Comments Impedance Zo = 50 Ω +/- 10% CPURST# Spacing to other signals 3 X trace width.
Page 271 Max=0.8 in plane Trace Width: Route groups of signals on the Total Trace Length (TTL) Brakeout Trace Width 4 mils same layer from EP80579 to the 2.0 in - 6.0 in DDR_A[14:0], farthest DIMM. Stripline: 6.5 mils(L3/L8) DDR_BA[2:0], Termination Trace Length...
Page 272 ® Intel EP80579 Integrated Processor Product Line—Layout Checklist Table 97. Layout Checklist (Sheet 4 of 13) Trace Geometry and Signal Name Length Requirements Comments Impedance Section 9.7, “DDR2 Interface EP80579 to First DIMM System Interconnect”. 2.0 in to 4.0 in Max...
Page 273 ® Layout Checklist—Intel EP80579 Integrated Processor Product Line Table 97. Layout Checklist (Sheet 5 of 13) Trace Geometry and Signal Name Length Requirements Comments Impedance Ω Zdiff = 90 +/- 10% Trace Width: Brakeout Trace Width 4 mils Microstrip: 4.75 mils Stripline: 4.5 mils (L3/L8)
Page 274 ® Intel EP80579 Integrated Processor Product Line—Layout Checklist Table 97. Layout Checklist (Sheet 6 of 13) Trace Geometry and Signal Name Length Requirements Comments Impedance GP3_PIRQF# Zo = 50 Ω +/- 10% Ω GP4_PIRQG# Zo = 50 +/- 10% Ω...
Page 275 Stripline: 20 mils SATA_RBIAS Routing Length LT: Place the RBIAS (resistor bias) Ω Zo = 50 +/- 10% as close as possible to EP80579 SATA_RBIAS# Max = 0.5 in. ® Intel EP80579 Integrated Processor Product Line May 2010 Order Number: 320068-005US...
Page 276 ® Intel EP80579 Integrated Processor Product Line—Layout Checklist Table 97. Layout Checklist (Sheet 8 of 13) Trace Geometry and Signal Name Length Requirements Comments Impedance Zdiff = 100 Ω +/- 10% Trace Width: Brakeout Trace Width 4 mils Microstrip: 4 mils Routing Length LT: Stripline: 3.75 mils (L3/L8)
Page 277 ® Layout Checklist—Intel EP80579 Integrated Processor Product Line Table 97. Layout Checklist (Sheet 9 of 13) Trace Geometry and Signal Name Length Requirements Comments Impedance Ω THRMTRIP# Zo = 50 +/- 10% Ω SLP_S3# Zo = 50 +/- 10% Ω...
Page 278 ® Intel EP80579 Integrated Processor Product Line—Layout Checklist Table 97. Layout Checklist (Sheet 10 of 13) Trace Geometry and Signal Name Length Requirements Comments Impedance Zo = 55 Ω +/- 10% Trace Width: Breakout: Brakeout Trace Width 4 mils EP80579 Max = 500mils.
Page 279 Zo = 50 +/- 10% Time Division Multiplexing (TDM) Interface Note: Certain EP80579 SKUs may not contain this feature. Feature must be enabled with EP80579 Software. See EP80579 “SKU Features” in the EP80579 Software Documentation for detailed Information Ω Rx_CLK[2:0]...
Page 280 ® Intel EP80579 Integrated Processor Product Line—Layout Checklist Table 97. Layout Checklist (Sheet 12 of 13) Trace Geometry and Signal Name Length Requirements Comments Impedance Zo = 50 Ω +/- 10% Trace Width: Brakeout Trace Width 4 mils Breakout: Max = 1 in.
Page 281: Ck410 Layout Checklist
® Layout Checklist—Intel EP80579 Integrated Processor Product Line Table 97. Layout Checklist (Sheet 13 of 13) Trace Geometry and Signal Name Length Requirements Comments Impedance Ω TSYNC_TX_SNAP Zo = 50 +/- 10% Miscellaneous I/O Interface JTAG Section 26.3.1, “JTAG Ω...
Page 282: Ck410 Schematic Checklist
® Intel EP80579 Integrated Processor Product Line—Layout Checklist Table 98. CK410 Schematic Checklist Trace Geometry and Signal Name Length Requirements Comments Impedance Note: See CK410 Clock Synthesizer/Driver Specification for more details Ω PCIF_0/ITP_EN Zo = 50 +/- 10% PCIF_1, Ω...
Page 283: Schematics Checklist
28.0 Schematics Checklist The schematic checklist provides design recommendations and guidance for the development of EP80579-based platform designs. See the individual peripheral interface chapters in this document for further details. Note: Some of the information in this document may not be applicable if a customer design implementation deviates from what was implemented in the Development Board.
Page 284: Schematic Checklist
EP80579 CPU monitoring circuitry if used. temperature. It is used to control the fan speeds of the EP80579 heat sink. If this feature is not used, the heat sink fan can be connected to operate at a constant speed, and...
Page 285 AND of PWROK by a debug tool. CPUPWRGD_OUT O (OD) and VRMPWRGD signals. • Pull up signal to EP80579 3.3V (VCC33) using a 10KΩ ± 5% Note: resistor . • Pull up signal to EP80579 3.3V (VCC33) using a 10KΩ ± 5% resistor if not used.
Page 286 • Connect to GPIO[40] to be external error signal (for example, NMI) used as IOAPIC IRQ35 by EP80579. The IA-32 core keeps • Pull-up to EP80579 3.3V IERR# asserted until the assertion of IERR#...
Page 287 ® Intel EP80579 Integrated Processor Product Line—Schematics Checklist Table 100. Schematic Checklist (Sheet 4 of 26) I/O Type Checklist Items Recommendations Comments (Default) • Connect DDR_CK[2:0]/ DDR_CK[2:0]# from EP80579 DDR_CK[5:0], to DIMM0. • See Figure 79 Figure 80 DDR_CK[5:0]# • Connect DDR_CK[5:3]/ •...
Page 288 ® Schematics Checklist—Intel EP80579 Integrated Processor Product Line Table 100. Schematic Checklist (Sheet 5 of 26) I/O Type Checklist Items Recommendations Comments (Default) Note: • Connect to one of 100 MHz • Connect PEA_CLK(p/n) to a differential clock outputs from...
Page 289 EP80579 interprets this strap as • This signal can function as either follows: GPIO[16] or IRQ[24]. • 0 = EP80579 does not invert GP16_IRQ24 • Resides in Core Power Well • 50KΩ internal pull-up. • 1 = EP80579 inverts A16 on...
Page 290 ® Schematics Checklist—Intel EP80579 Integrated Processor Product Line Table 100. Schematic Checklist (Sheet 7 of 26) I/O Type Checklist Items Recommendations Comments (Default) • 50KΩ internal pull-up • No external Pullup Required • • Input/Output configurable if used as GPIO[18].
Page 291 ® Intel EP80579 Integrated Processor Product Line—Schematics Checklist Table 100. Schematic Checklist (Sheet 8 of 26) I/O Type Checklist Items Recommendations Comments (Default) • No external pull-up required if used in IRQ mode. • Input/Output configurable if used as GPIO[27].
Page 292 • Can be left as NC when the port is through a 15 Ω SPI_MOSI • Connect signal not connected to an interfacing ±1% series resistor device. • Place resistor close to EP80579 ® Intel EP80579 Integrated Processor Product Line May 2010 Order Number: 320068-005US...
Page 293 ® Intel EP80579 Integrated Processor Product Line—Schematics Checklist Table 100. Schematic Checklist (Sheet 10 of 26) I/O Type Checklist Items Recommendations Comments (Default) • Connect to the serial data Note: output pin of the flash device • Must be pulled high to 3.3V through through a 15 Ω...
Page 294 ® Schematics Checklist—Intel EP80579 Integrated Processor Product Line Table 100. Schematic Checklist (Sheet 11 of 26) I/O Type Checklist Items Recommendations Comments (Default) • SMBus Intruder Detect: Detects if the system case has been opened. Can be set to disables the system if •...
Page 295 ® Intel EP80579 Integrated Processor Product Line—Schematics Checklist Table 100. Schematic Checklist (Sheet 12 of 26) I/O Type Checklist Items Recommendations Comments (Default) • UART Port[2:1] Data Terminal Ready: When low, these pins inform the modem or data set that the UART ports are ready to establish a communication link.
Page 296 ® Schematics Checklist—Intel EP80579 Integrated Processor Product Line Table 100. Schematic Checklist (Sheet 13 of 26) I/O Type Checklist Items Recommendations Comments (Default) • UART Port[2:1]Serial Data Input: Serial data input form external devices to the receive UART port [2:1].
Page 297 ® Intel EP80579 Integrated Processor Product Line—Schematics Checklist Table 100. Schematic Checklist (Sheet 14 of 26) I/O Type Checklist Items Recommendations Comments (Default) Serial ATA LED: This is an open- collector/open-drain output signal driven during SATA command activity. It is to be connected to external circuitry that can provide the current to drive a •...
Page 298 Recommendations Comments (Default) • Can monitor using an LED to indicate IA-32 core Thermal Status. Thermal Alarm. Driven out by EP80579. PROCHOT# Monitored by Platform. • Pull up signal to EP80579 VCC33 (3.3V) using a 10KΩ ± 5% resistors • Monitor using an LED to indicate IA-32 core Thermal Status.
Page 299 ® Intel EP80579 Integrated Processor Product Line—Schematics Checklist Table 100. Schematic Checklist (Sheet 16 of 26) I/O Type Checklist Items Recommendations Comments (Default) • Suspend State Status: Asserted to indicate that the system is entering into a low power state.
Page 300 • GBE Port 0 supports Wake-On-LAN (WOL); hence GBE Port 0 Block resides in the Sustain Power Well within EP80579. It is required that all GBE Port 0 (Transmit/Receive) interface signals on the platform be powered by GBE Standby Voltage. GBE Port 1&2 should be powered by GBE core power.
Page 301 ® Intel EP80579 Integrated Processor Product Line—Schematics Checklist Table 100. Schematic Checklist (Sheet 18 of 26) I/O Type Checklist Items Recommendations Comments (Default) RGMII Mode • Interconnect each Port Transmit Clock (GBEn_TxCLK) to the corresponding Port Transmit Clock of the RGMII PHY Device RMII Mode •...
Page 302 ® Schematics Checklist—Intel EP80579 Integrated Processor Product Line Table 100. Schematic Checklist (Sheet 19 of 26) I/O Type Checklist Items Recommendations Comments (Default) RGMII Mode • Interconnect each Port Receive Clock (GBEn_RxCLK) to the corresponding Port Receive Clock of the RGMII PHY Device •...
Page 303 ± 5% resistor MDIO Note: • Must be pulled high through a 10 KΩ resistor to EP80579 GbE 2.5V Standby (VCCSUS25) when none of GBE ports is connected to an interfacing device • Connect to EEPROM Serial Data Output signal (DO) •...
Page 304 • Connect to SYS_PWR_OK if standby voltages are not generated. 3-Port Time Division Multiplexing (TDM) Interface Note: Certain EP80579 SKUs may not contain this feature. Feature must be enabled with EP80579 software. See EP80579 “SKU Features” in the EP80579 Software Documentation for detailed information. Rx_CLK[2:0], •...
Page 305 ® Intel EP80579 Integrated Processor Product Line—Schematics Checklist Table 100. Schematic Checklist (Sheet 22 of 26) I/O Type Checklist Items Recommendations Comments (Default) • The LEB controller allocates up to 256 MB of memory space to support • Expansion Bus Address.
Page 306 ® Schematics Checklist—Intel EP80579 Integrated Processor Product Line Table 100. Schematic Checklist (Sheet 23 of 26) I/O Type Checklist Items Recommendations Comments (Default) Expansion Bus Target Chip Selects: Chip selects to select Expansion Bus devices. • Devices using EX_CS[3:0]# indicate Data Ready with EX_IOWAIT# •...
Page 307 ® Intel EP80579 Integrated Processor Product Line—Schematics Checklist Table 100. Schematic Checklist (Sheet 24 of 26) I/O Type Checklist Items Recommendations Comments (Default) • These signals are used to halt accesses using expansion bus chip selects 7 through 4 when the chip selects are configured to operate in HPI mode.
Page 308 ® Schematics Checklist—Intel EP80579 Integrated Processor Product Line Table 100. Schematic Checklist (Sheet 25 of 26) I/O Type Checklist Items Recommendations Comments (Default) Pull-up to Platform 1.2V (V1P2) supply through a 51Ω ±5% resistor Pull-up to Platform 1.2V (V1P2) supply through a 51Ω ±5% resistor Pull-down to ground through a 51Ω...
Page 309 ® Intel EP80579 Integrated Processor Product Line—Schematics Checklist Table 100. Schematic Checklist (Sheet 26 of 26) I/O Type Checklist Items Recommendations Comments (Default) • Must have a 330Ω pull-up to VCCPSUS (EP80579 3.3V sustain power) if used to connect to TESTIN# signal on Reserved10 the ITP Debug Port.
Page 310: Power Supply Decoupling
® Schematics Checklist—Intel EP80579 Integrated Processor Product Line 28.3 Power Supply Decoupling Table 101. Decoupling Recommendations (Sheet 1 of 3) Power/Ground Type Configuration Decap Component Layout Notes Pin Name IA-32 core and Logic Power 150 µF 1.2V core logic power 10 µF...
Page 311 ® Intel EP80579 Integrated Processor Product Line—Schematics Checklist Table 101. Decoupling Recommendations (Sheet 2 of 3) Power/Ground Type Configuration Decap Component Layout Notes Pin Name 3.3V SATA power supply VCCSATA33 • Connect to VCC33 power supply(3.3V) 3.3V GbE power supply VCCGBE33 •...
Page 312: Ck410 Schematic Checklist
® Schematics Checklist—Intel EP80579 Integrated Processor Product Line Table 101. Decoupling Recommendations (Sheet 3 of 3) Power/Ground Type Configuration Decap Component Layout Notes Pin Name Bandgap Power Pins with Filter Note: Section 6.6.5 Table 13 for Bandgap Filter guidelines 3.3V SATA Bandgap power...
Page 313 • This pin works in conjunction with FS_A and • If BSEL = 0 (FSB = FS_B to select the CPU clock frequency. 400MTS), connect to • Connect using EP80579 BSEL signal to select VCC3 through 1KΩ FS_C/TEST_SEL EP80579 FSB frequency ±1% resistor...
Page 314 ® Schematics Checklist—Intel EP80579 Integrated Processor Product Line Table 102. CK410 Schematic Checklist (Sheet 3 of 3) System Series Pin Name Recommendations Pull-up/Pull-down Resistor • Connect to a 14.318-MHz crystal, placed within 500 mils of CK410 device. XTAL_IN/XTAL_OUT • It is recommended to use 33 pF external load capacitors •...
Page 315: Reference Design
EP80579 Integrated Processor Product Line—Reference Design 29.0 Reference Design The EP80579 reference design includes the Development Board schematics, BOMs (Bill Of Materials), and other CAD board files. Contact your Intel field representative to obtain these documents. ® Intel EP80579 Integrated Processor Product Line...
Page 316: System Memory Interface (Sodimm)
The targeted specification for the unbuffered SODIMM DDR2- 400/533/667/800 with EP80579 will be based on 256 MB, 512 MB, 1 GB, and 2 GB memory technology. Unbuffered SODIMM DDR2-400/533/667/800 design on EP80579 has NOT been validated by Intel and the data provided in these guidelines are the results from simulation only.
Page 317: Terminology And Definitions
Single-sided memory modules are always single-rank. Double-sided unbuffered and registered DIMMs are always dual-rank. Supported Configurations Table A-2 shows the various DDR2 SODIMM memory configurations, including capacities and technologies, supported by the EP80579. Table A-2. Supported SODIMM Memory Capacity for 64-bit Mode Technology Total DRAM...
Page 318: Sodimm System Memory Design Guidelines
A.4.1 SODIMM DDR2 Signal Groups The EP80579 has a single channel memory interface. The channel consists of 64 data bits with no ECC support. The pinout for the channel has been optimized for a baseboard design with one SODIMM.
Page 319: Ddr2 Signal Groups
® System Memory Interface (SODIMM)—Intel EP80579 Integrated Processor Product Line Table A-4. DDR2 Signal Groups Group Signal Name Description Data, Mask, & Strobe DDR_DQ[0..7], Byte 0 DDR_DM0, & Data Byte Lane0 DDR_DQS0/DQS0# DDR_DQ[8..15], Byte 1 DDR_DM1, & DQS1/ Data Byte Lane1 DDR_DQS1# DDR_DQ[16..23],...
Page 320: Length Matching Formulas Between Ep80579 And Ddr2 Sodimm
A-4. The Command/Address and Control signals require external terminations. External terminations are not required for DQ and DQS signals since both the EP80579 and the SDRAMs contain internal ODT. The following sections provide the detailed topology and routing guidelines for each of the signal groups.
Page 321: Ddr2 Interfaced System Interconnect
® System Memory Interface (SODIMM)—Intel EP80579 Integrated Processor Product Line Figure A-1. DDR2 Interfaced System Interconnect DDR2_VTT SODIMM Command/Address EP80579 CS0#, CKE0, ODT0 CS1#, CKE1, ODT1 CLK0 / CLK0# DDR2 CLK1 / CLK1# Memory Controller DQS[7:0]/DQS#[7:0] DQ[63:0], DM[7:0]] A.4.5 Topologies and Routing Guidelines A.4.5.1...
Page 322: Data/Mask/Strobe Signal Routing Topology Diagram
® Intel EP80579 Integrated Processor Product Line—System Memory Interface (SODIMM) Figure A-2. Data/Mask/Strobe Signal Routing Topology Diagram EP80579 SODIMM EP80579 EP80579 EP80579 Breakin Package Board Breakout Routing Trace Routing Routing BREAKIN BREAKOUT ROUTE Table A-6. Data and Strobe Signal Group Routing Guidelines (Sheet 1 of 2)
Page 323 ROUTE BREAKIN = Max TTL (DQ/DM) - 200 mils ® See the Intel EP80579 Integrated Processor Product Line Datasheet for package length information. B = 0.8 in (max) BREAKOUT C = 1.0 in - 4.0 in ROUTE D = 0.8 in (max)
Page 324: Ddr2 Point-To-Point Clock Routing Diagram
The clock signal group for the SODIMM comprises of two differential clock pairs. The differential clock pairs must be point-to-point routed from the EP80579 to the SODIMM and must maintain the correct isolation spacing from other signals. Additionally, it is important to maintain the correct spacing and length matching between the pair to protect the differential integrity.
Page 325: Write Operation Odt Table
A.4.5.3 DDR2 Control Signals – DDR_CS[1:0]#, DDR_ODT[1:0], DDR_CKE[1:0] In the EP80579 memory configuration, the DDR_CKE, DDR_ODT, and DDR_CS# signals make up the control signal group. EP80579 provides six signals: DDR_CS[1:0]#, DDR_ODT[1:0], and DDR_CKE[1:0] as control signals for two-rank memory support.
Page 326: Ddr2 Control Signals- Implementation
® Intel EP80579 Integrated Processor Product Line—System Memory Interface (SODIMM) Table A-9. Read Operation ODT Table SODIMM Write Controller SODIMM Module Target Configuration Configuration Rank0 Rank1 1-Rank (SR) Rank0 120 Ω ODT Off 2-Rank (DR) Rank0 120 Ω ODT Off 150 Ω...
Page 327: Ddr2 Control Signal Group Routing Guidelines
(MA[14:0]), 3 bank addresses (BA[2:0]), row address select (RAS#), column address select (CAS#), and write enable (WE#). The address/ command signals are “clocked” into the SODIMM using the positive edge of the differential clock signals. The EP80579 drives the address/command and clock signals together. ®...
Page 328: Address/Command With Parallel Termination Topology Diagram
® Intel EP80579 Integrated Processor Product Line—System Memory Interface (SODIMM) Resistor packs are acceptable for the parallel (R ) address/command termination resistors, but address/command signals cannot be routed to the same resistor pack (RPACK) used by data, data strobe, or control signals.
Page 329 The DDR_SLWCRES, DDR_RCOMPX, DRV_CRES, and DDR_CRES0 signals are compensation resistors for slew rate, impedance, and common return, respectively. Intel recommends 20 mil wide traces with a minimum spacing of 12 mils from other signals. When breaking out from the EP80579, maintain a minimum spacing of 4.5 mils up to a maximum length of 500 mils.
Page 330: Ddr_Slwcres, Ddr_Rcompx, Ddv_Cres, & Ddr_Cres0 Routing Topology
Figure A-7). Intel recommends 20 mil wide traces with a minimum spacing of 12 mils from other signals. When breaking out from the EP80579, maintain a minimum spacing of 4.5 mils spacing up to a maximum length of 500 mils.
Page 331: Decoupling Recommendations
Finally, the DDR_VREF signal must be routed with as wide a trace as possible. Table A-13 provides the routing and component guidelines for the Vref circuit. Intel recommends at least a 20 mil wide trace with a minimum spacing of 12 mils from other signals. Figure A-8. DDR_VREF Generation Example Circuit V1P8_DDR 49.9 Ω,...
Page 332: Clock Delay Programming And Write Levelization
Intel EP80579 Integrated Processor Product Line—System Memory Interface (SODIMM) Note: These decoupling recommendations are for the EP80579 pins. Place multiple capacitors in parallel to get the desired value for capacitance and ESL. Clock Delay Programming and Write Levelization The EP80579 primary memory clocks CK[1:0]/CK[1:0]# have write levelization circuitry, WDLL.
Page 333: System Memory Interface (Memory Down)
Note: Unbuffered or registered memory down DDR2-400/533/667/800 design configurations on EP80579 has NOT been validated by Intel and the data provided in these guidelines are the results from simulation for single rank topologies only. Usage of any of the simulation models, topology, and guidelines described in this document should be accompanied with simulations in your own environment to ensure that your implementation will be successful.
Page 334: Supported Configurations
® System Memory Interface (Memory Down)—Intel EP80579 Integrated Processor Product Line Table B-16. DDR Terminology (Sheet 2 of 2) Acronym Description/Comment Minimum number of column locations on any row and are accessed by a single Page size ACTIVATE command DRAM devices Multiple DRAM devices together make up a DIMM.
Page 335: Dram Addressing
256 Mb 256 MB 512 Mb 512 MB 1 Gb 2 Gb Note: In the 32b mode, all EP80579 unused data bus bits (DQ[63:33]/DQS[7:4]/DM[7:4]) should be pulled high through 10 Kohm resistors. DRAM Addressing Table B-20, Table B-21, Table B-22...
Page 336: Ddr2 Signal Groups
Table B-24 summarizes the different signal groupings of the DDR interface. See the ® Intel EP80579 Integrated Processor Product Line Datasheet for more details on specific pin functionality. Table B-24. DDR2 Signal Groups (Sheet 1 of 2) Group Signal Name Description Data, Mask, &...
Page 337: Supported Memory Configurations
Voltage Reference (Analog) Supported Memory Configurations The EP80579 Memory Controller supports up to 4 GB of 400/533/667/800 MT/s memory in a one-rank (2 GB) or two-rank (4 GB) configuration. However, since 9 (8 Data +1 ECC) x8 devices are required for each rank, only single rank designs are reasonably feasible in the memory down implementations.
Page 338: Overview And Design Considerations
A simplified summary of the length matching formulas from the EP80579 to the Memory Down devices for each signal group is provided in Table B-26.
Page 339 GND pins on the SDRAM pin and will need to have a contiguous return path back to EP80579. If a power plane is referenced instead, ensure that a minimum of four AC stitching capacitors are used near the SDRAM devices’...
Page 340: Ddr2 Clock Signal Routing Topology (One Clock For Three Devices)
® System Memory Interface (Memory Down)—Intel EP80579 Integrated Processor Product Line clock interconnect between the EP80579 and the memory devices. Table B-27 provides the clock distribution among the memory devices, and Table B-28 provides the clock routing guidelines. Table B-27. Clock to Memory Device Mapping...
Page 341 ® Intel EP80579 Integrated Processor Product Line—System Memory Interface (Memory Down) Table B-28. Clock Signal Group Routing Guidelines (Sheet 2 of 2) Parameter Routing Guidelines Figure Stripline Board Route • Trace Length = 1.5 in (min) - 4.0 in (max) Stripline Board Route •...
Page 342: Ddr2 Data/Dm/Ecc Byte Lane Topology
® System Memory Interface (Memory Down)—Intel EP80579 Integrated Processor Product Line Figure B-10. DDR2 Data/DM/ECC Byte Lane Topology EP80579 SDRAM Stripline Routing Microstrip Routing Figure B-11. DDR2 Data Strobe Routing (DQS/DQS#) Topology (One Strobe per Byte Lane) SDRAM EP80579 Stripline/Microstrip Routing Microstrip Routing Table B-29.
Page 343 ® Intel EP80579 Integrated Processor Product Line—System Memory Interface (Memory Down) Table B-29. Data and Strobe Signal Group Routing Guidelines (Sheet 2 of 2) Routing Guidelines Figure Parameter Data Byte Lane Data & Data Mask Strobe • Inter-pair Spacing:-- DQS/DQS# = 6 mils...
Page 344: Ddr2 Address, Command And Control Signal Routing Topology
DDR2-SDRAM address, command and control signals. A maximum of 6 vias should be used for layer changes over the entire route from the EP80579 pin to SDRAM pin. Figure B-12. DDR2 Address, Command and Control Signal Routing Topology...
Page 345: B-31 Ddr2 Address/Command Signal Group Routing Guidelines
® Intel EP80579 Integrated Processor Product Line—System Memory Interface (Memory Down) Table B-31. DDR2 Address/Command Signal Group Routing Guidelines Parameter Routing Guidelines Figure DDR_MA[14:0], DDR_BA[2:0], DDR_RAS#, Signal Group DDR_CAS#, DDR_WE#, DDR_CS[0]#, DDR_CKE[0], DDR_ODT[0] Reference Plane Ground Referenced Layer Assignment • Signals must be routed on the same layer Characteristic Trace Impedance (Zo) 45 Ω...
Page 346: Ddr_Slwcres, Ddr_Rcompx, Ddv_Cres, & Ddr_Cres0 Routing Topology
The DDR_SLWCRES, DDR_RCOMPX, DRV_CRES, and DDR_CRES0 signals are compensation resistors for slew rate, impedance, and common return, respectively. Intel recommends 20 mil wide traces with a minimum spacing of 12 mils from other signals. When breaking out from the EP80579, maintain a minimum spacing of 4.5 mils up to a maximum length of 500 mils.
Page 347 ® Intel EP80579 Integrated Processor Product Line—System Memory Interface (Memory Down) Figure B-14. DDR_CRES1 and DDR_CRES2 Signal Connections VCC18 DDR_CRES2 100 Ω 0.1uF DDR_CRES1 100 Ω ® Intel EP80579 Integrated Processor Product Line Platform Design Guide May 2010 Order Number: 320068-005US...

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