General Design Considerations; High Power/Low Power Mixed Architecture; High Power/Low Power Mixed Suspend/Core Power Well Architecture - Intel EP80579 Manual

System Management Bus (SMBus) Interface—Intel
Line
• Amount of current available in the suspend power well (i.e., minimizing the load of
the suspend power well)
13.1.2

General Design Considerations

The following are general design considerations:
• The pull-up resistor size for the SMBus data (SMBDATA) and clock (SMBCLK)
signals is dependent on the bus load, which includes leakage currents for all
devices. Generally the SMBus device that can sink the least amount of current is
the limiting agent on how small the resistor can be. The pull-up resistor cannot be
made so large that the bus time constant (
SMBus rise and time specification.
• The maximum bus capacitance that a physical segment can reach is 400 pF.
• SMBus devices that can operate in STR (Suspend-to-RAM) must be powered by the
suspend power well.
• SMBus address contention as a design consideration.
2
• I C devices should be powered by the appropriate core power well voltage. During
2
an I
device may not release the SMBus if EP80579 receives an asynchronous reset. By
using the core power, the BIOS is able to reset the device if necessary. SMBus 2.0-
compliant devices have a time-out capability that makes them insusceptible to this
2
I C issue, allowing flexibility in choosing a voltage supply.
• If SMBus is connected to PCI Express, it must be connected to all PCI Express slots.
13.1.3

High Power/Low Power Mixed Architecture

This design allows for current isolation of high and low current devices while also
allowing SMBus devices to communicate while in S3. Leakage in the suspend power
well is minimized by keeping non-essential devices connected to the core power well.
This is accomplished by the use of a FET to isolate the devices powered by the core and
suspend power wells. See
Figure 120. High Power/Low Power Mixed Suspend/Core Power Well Architecture
N o n - S ta n d b y
D e v ic e s
V c c V c c
S M B u s
Additional considerations for mixed architecture are shown below:
• The bus bridge must be powered by a voltage from the suspend power well.
• Devices that are powered by the suspend power well must not drive into other
devices that are powered off. This is accomplished with the "bus switch."
• The bus bridge can be a device similar to the Phillips* PCA9515, used on the
Development Board.
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product
C transaction, in which the device is sending information to EP80579, the
Figure
D e v ic e s ru n n in g
in S t a n d b y
V C C P S U S
B u ffe re d P o w e r
G o o d S ig n a l F ro m
P o w e r S u p p ly
L o w
C u r r e n t
×
Resistance Capacitance
120.
D e v ic e s ru n n in g
V c c S u s V c c S u s
B u s
B rid g e
E P 8 0 5 7 9
) does not meet the
N o n - S t a n d b y
in S ta n d b y D e v ic e s
V C C P S U S V c c
S M B u s S M B u s
B u ffe r e d P o w e r
G o o d S ig n a l F ro m
P o w e r S u p p ly
H ig h
C u r r e n t
B 6 3 9 1 - 0 1
May 2010
V c c
179