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Layout Checklist—Intel
EP80579 Integrated Processor Product Line
Table 97.
Layout Checklist (Sheet 9 of 13)
Signal Name
THRMTRIP#
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
PWRBTN#
RI#
SYS_RESET#
RSMRST#
SUS_STAT#
SUSCLK
VRMPWRGD
IERR#
CLK14
WDT#
Controller Area Network (CAN) Interface
CAN0TXD,
CAN1TXD
CAN0TXEN,
CAN1TXEN
CAN0RXD,
CAN1RXD
Gigabit Ethernet (GbE) Interface
GBE0_TxCLK,
GBE1_TxCLK
GBE2_TxCLK
®
Intel
EP80579 Integrated Processor Product Line
Order Number: 320068-005US
Trace Geometry and
Impedance
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
IICH Miscellaneous Signals
Ω
Zo = 50
+/- 10%
Trace Width:
Microstrip: 5.5 mils
Stripline: 4.5 mils (L8)
Airgap Spacing:
Spacing to other signals
Min = 10mils
Spacing to non clock signals
Min = 10mils
Ω
Zo = 50
+/- 10%
Acceleration and I/O Complex (AIOC)
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 55
+/- 10%
Trace Width:
Brakeout Trace Width 4 mils
Microstrip: 4.5 mils
Stripline:
3.75 mils (L3/L8)
5 mils (L5/L6)
Airgap Spacing:
Brakeout spacing Min=4mils
Spacing to other clock signals
Stripline Min = 20mils
Microstrip Min = 25mils
Length Requirements
Breakout:
Max = 500mils.
Place damping resistor as close
as possible to the source.
Length LT:
Max = 18 in.
Breakout:
EP80579 Max = 500mils.
PHY Max = 300mils.
See
Transmit Clock
Total Clock Routing:
Place pull-up resistors close to
Microstrip 1.5 to 7.8 in
PHY device
Stripline 1 to 7.8 in.
Pull Up Trace Length
Max=0.4 in.
Comments
Section 19.6.1.1, "GbE
Topology".
May 2010
277
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