Ck410 Layout Checklist - Intel EP80579 Manual

®
Layout Checklist—Intel EP80579 Integrated Processor Product Line
Table 97. Layout Checklist (Sheet 13 of 13)
Signal Name
TSYNC_TX_SNAP
JTAG
TMS
TDI
TDO
TCK
TRST#
BPM3_IN
BPM4_PRDY_OUT
BPM5_PREQ_IN
BPM[3:0]
Miscellaneous Pins
PME#
PCIRST#
SPKR
Reserved Pins
Reserved[20:0]
No Connect Pins
Note: (All No Connect Pins should be left un-connected)
NC_SUS_TWO
NC_TWO
NC7
NC[22:9]
NC[38:34]
NC[48:40]
NC[57:50]
27.3

CK410 Layout Checklist

For additional information, see the CK410 Clock Synthesizer/Driver Specification and
the component's datasheet.
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
Trace Geometry and
Impedance
Ω
Zo = 50 +/- 10%
Miscellaneous I/O Interface
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Zo = 50 Ω +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Length Requirements
See
Routing
See
Routing
See
Routing
See
Routing
See
Routing
See
Routing
See
Routing
See
Routing
See
Routing
Comments
Section 26.3.1, "JTAG
Guidelines".
Section 26.3.1, "JTAG
Guidelines".
Section 26.3.1, "JTAG
Guidelines".
Section 26.3.1, "JTAG
Guidelines".
Section 26.3.1, "JTAG
Guidelines".
Section 26.3.1, "JTAG
Guidelines".
Section 26.3.1, "JTAG
Guidelines".
Section 26.3.1, "JTAG
Guidelines".
Section 26.3.1, "JTAG
Guidelines".
May 2010
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