Pci Express Down Device Routing (Ep80579 Receive) - Intel EP80579 Manual

• L2 starts from the EP80579 breakout region to the PCI Express device breakout
region.
• L3 is the breakout region of the PCI Express device.
• LT is the main routing section that is from the EP80579 pin to the PCI Express
device.
Table 54.

PCI Express Down Device Routing (EP80579 Receive)

Signal Group
Reference Plane
Layer Assignment
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing within a pair from
edge to edge
Nominal Trace Spacing from edge of one
differential pair to edge of another
differential pair
Trace Length L1, L1'– EP80579 Breakout
region
Trace Length L2, L2' – edge of EP80579
Breakout region to edge PCI Express
Device breakout region.
Trace Length L3, L3' – PCI Express
breakout region.
Trace Length LT– EP80579 pin to PCI
Express connector
Length Tuning Requirements
Figure 95.

PCI Express Down Device Routing (EP80579 Receive)

®
Intel EP80579 Integrated Processor Product Line
Platform Design Guide
147
®
Intel EP80579 Integrated Processor Product Line—PCI Express* Interface
Parameter
PEA0_Tn[7:0], PEA0_Tp[7:0]
Ground Referenced
Layers 3 or 8 (stripline)
Layers 1 or 10 (microstrip)
90 Ω ±10% (Differential)
4.5 mils (stripline)
4.75 mils (microstrip)
5.5 mils (stripline)
5.25 mils (microstrip)
The greater of:
Min = 0.75 in.
Max = 2.5 in.
Min = 4.0 in (stripline)
Min = 2.5 in (microstrip)
Max = 14.5 in. (stripline)
Max = 13.0 in. (microstrip)
Min = 0.75 in.
Max = 2.0 in.
LT = L1 + L2 +L3
Routing must remain on the same layer.
Maximum number of vias is 4.
LT-LT' = ±5 mils
LT = L1+L2+L3
L1
EP80579
L1'
Routing Guidelines
• 18 mils or 3x dielectric thickness (stripline)
• 20 mils or 3x dielectric thickness
(microstrip)
PCI
L2
L3
Express*
Device
L2'
L3'
Figure
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Figure 87
Figure 88
Figure 87
Figure 88
Figure 87
Figure 88
Figure 95
Figure 95
Figure 95
Figure 95
Figure 95
May 2010
Order Number: 320068-005US